Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

use"clock enable " instead of gated clock ?

Status
Not open for further replies.

bravobravo

Full Member level 2
Joined
May 16, 2001
Messages
122
Helped
3
Reputation
6
Reaction score
2
Trophy points
1,298
Location
USA
Activity points
973
use"clock enable " instead of gated clock ?
 

darkness

Newbie level 4
Joined
Jan 15, 2003
Messages
7
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
52
gated clocks

Gating clocks is a tecnique "dangerous" but usefull in very low power Application Specific IC: for example it is used in Pacemaker Chips.
 

rx300

Member level 3
Joined
Mar 2, 2002
Messages
60
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
650
Re: gated clocks

In multi-million gates SoC designs, gated clock is almost mandatory. It custs down power significantly. Without clock gating, the chip will definitely melt.

Clock enable is basically a mux where one input is feedback. The flops in Xilinx devices already have this mux built in. It's natural to take advantage of it.
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top