nee_naresh04
Member level 2
hi fnds I AM DOING AN ASIC PROJECT NOW I DIDN'T HAVE SYNOPSIS CAD TOOLS HERE.SO I WILL PROVIDE THE .sch FILE OF xILINX..THEN ANY ONE CAN TRANSILATE THAT INTO HDL BY USING Xilinx as well as Synopsis..
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library ieee;
use ieee.std_logic_1164.all;
entity plasample is
port (
xlxn_37, xlxn_38, xlxn_39, xlxn_40, xlxn_41, xlxn_43 : in std_logic;
xlxn_50, xlxn_51 : out std_logic);
end plasample;
architecture behave of plasample is
signal nand0, nand1, nand2, nand3, nand4, nand5 : std_logic;
begin -- behave
nand0 <= (xlxn_37 nand xlxn_39) nand xlxn_40;
nand1 <= (xlxn_37 nand xlxn_39) nand xlxn_41;
nand2 <= (xlxn_37 nand xlxn_40) nand xlxn_43;
nand3 <= (xlxn_37 nand xlxn_41) nand xlxn_43;
nand4 <= (xlxn_38 nand xlxn_39) nand xlxn_40;
nand5 <= (xlxn_38 nand xlxn_39) nand xlxn_41;
xlxn_50 <= (nand0 nand nand3) nand nand5;
xlxn_51 <= (nand0 nand nand1) nand (nand2 nand nand4);
end behave;