urgent- methods to reduce lock in time of PLL

[mggayathrimg]

What are the methods to reduce lock in time of PLL? Will the logic with coarse and fine PFD reduce the lock in time and improve the performance??
Can you suggest a logic to switch between coarse and fine PFD??

 

[Tunelabguy]

Have you already optimized the PLL feedback transfer function? Adding a little lead compensation (high-pass filtering) often helps tremendously. Google "PID loops". You might need more "D" in your PID.

 

[edick]

What I remember doing back in the analog days was changing the time constant of the error amplifier/charge-pump with an analog switch between two cap's. That worked rather well. Now, I was in the 1-to 10 MHz range at the time, but the method is sound. The key is to figure out when you're "close enough" to locked so you can then switch the loop bandwidth. That way you'll track better.