archgold
Newbie level 1
Hi, I need help writing a FIR Filter in Verilog.
The project is as follows:
Design and build a co-processor that interfaces to the Leon that implements an FIR filter. Use memory mapped registers on the AMBA APB bus device 12 to communicate with the co-processor. Your C program (and Modelsim Testbench) will transmit the 16 bit filter coefficients and the 16 bit filter inputs to the co-processor, and receive the 16 bit results computed by the co-processor. Assume that the maximum length of the filter is 163. Verify that your co-processor is working correctly in simulation and in hardware. Measure the MAC/s rate that this system can sustain. Compare this to software DSP in part 2a. Report required that covers both parts a) and b) of this project.
Hints:
1) Create a memory mapped register in the PSel12 space with the following format::
a. [2:0] – Op Code
i. InitRAM
ii. Convolve
iii. Load Coefficient
iv. Load Number of Taps
b. [18:3] – 16 bit data to be passed to FSM – InitRAM value, coefficients, filter inputs
c. [31] – Ready bit asserted by FSM indicating status – ready or busy.
Right now I am stuck try to create the Finite State Machine. I have the layout for my FSM and my block diagram drawn but am unable to actually write out the code. I have no idea what to do, can someone please help me?
The project is as follows:
Design and build a co-processor that interfaces to the Leon that implements an FIR filter. Use memory mapped registers on the AMBA APB bus device 12 to communicate with the co-processor. Your C program (and Modelsim Testbench) will transmit the 16 bit filter coefficients and the 16 bit filter inputs to the co-processor, and receive the 16 bit results computed by the co-processor. Assume that the maximum length of the filter is 163. Verify that your co-processor is working correctly in simulation and in hardware. Measure the MAC/s rate that this system can sustain. Compare this to software DSP in part 2a. Report required that covers both parts a) and b) of this project.
Hints:
1) Create a memory mapped register in the PSel12 space with the following format::
a. [2:0] – Op Code
i. InitRAM
ii. Convolve
iii. Load Coefficient
iv. Load Number of Taps
b. [18:3] – 16 bit data to be passed to FSM – InitRAM value, coefficients, filter inputs
c. [31] – Ready bit asserted by FSM indicating status – ready or busy.
Right now I am stuck try to create the Finite State Machine. I have the layout for my FSM and my block diagram drawn but am unable to actually write out the code. I have no idea what to do, can someone please help me?
