The glitches (spikes) will be due to transition times from 0~1 and 1~0 in your design.
It is not possible to get from a low logic state to a high logic state without some time passing. As seen in the waveforms at the bottom of the picture, the transitions take time.
Transition can be set to a minimum in some simulation software to provide nice-looking simulation graphs but does not reflect what really happens. Capacitance can be the cause.
I think additional logic can be added to remove the glitches.