Urgent: Divide an 8 bit input with a value without clock in verilog!!!

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xman24

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Hi..

I am using a divider block in which I dont have a clock. I need to divide the input which s 8 bit, with a value (say 8 ). so that the output of my divider will be divide by value(say 8 (value will be multiples of 2)) output.
I thought of a right shifter (for divide by 8, I will shift right 3 times) , and I implemented a 8 bit Barrell Shifter. But its giving rotate right shift :-(
if my input is 80(8 bit input) then after dividing value say 8 now, then output should be 8 which is a 8 bit value..
Please help.
 

For "multiples of 2". It will be 1/2/4/8/16/32 (case 1) .. or 2/4/6/8/10/12(case 2).
For case 1: you can just write a case statement is ok: the code will just have 8 or 9 lines.
casez(dividen[7:0] or divide[7:0])
8'b1zzz_zzzz: ouput = {7'h0, divide[7]};
8'b01zz_zzzz: output = {6'h0, divide[7:6]};
...
8'b0000_0001: output = divide[7:0]};
8'b0000_0000: this will be a error case
encase

For case 2: you really need a combination logic of a divider. YOu can call DesignWare IP or you can reference your FPGA tools.
 

Hey Thanks. Actually I need a divider block (without clock) which will divide the input ( 8 bit ) with divide value 320 and gives a output (8 bit). Please help.. Its urgent...
 

I don't know if 320 is a decimal or hex, but in either way, you don't need a divider block if dividing 8 bit data by 320 is what you are looking for, because the quotient is always 0, isn't it ?
Or are you expecting 8 bit output to be lesser than 1 ?
 
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