[URGENT]- Cordic Core(VHDL) simulation in modelsim

[saqib.shah06]

Hi everyone,

I need to compile a cordic core and simulate it in vhdl. I am using MODELSIM. I have the codes attached to this post.

Could someone tell me how to go about doing it?

I tried loading the fun_pkg.vhdl and cordic.vhd and then using a autogenerate compile order- i compiled both of them. Then I loaded the cordic_tb.vhd and compiled it. However after loading the waveforms, I get a very weird looking output with most signals in the "U" state.

Any help will be greatly appreciated!

 

[TrickyDicky]

It runs fine for me.

run these commands in modelsim:

vlib work
vcom fun_pkg.vhd
vcom cordic.vhd
vcom cordic_tb.vhd
vsim cordic

run 12 us

I notice that the clk and rst signals are never assigned in the testbench, but you use the tb_clk and tb_reset instead.

 

[saqib.shah06]

Thanks for your reply.

I did what you had mentioned exactly in your post, but I still some useless waveforms. After running the vsim cordic command, I added the cordic signals to the wave window by clicking add to wave > all items in region.

I have attached the output here.

It runs fine for me.

run these commands in modelsim:

vlib work
vcom fun_pkg.vhd
vcom cordic.vhd
vcom cordic_tb.vhd
vsim cordic

run 12 us

I notice that the clk and rst signals are never assigned in the testbench, but you use the tb_clk and tb_reset instead.

 

[TrickyDicky]

sorry, I meant
vsim cordic_tb