Upsampling a signal from UART

[Christian Chetcuti]

I have read in various literature books that the baud rate generator in a UART module should generate a signal whose sampling frequency is exactly 16 times the UART's designated baud rate.

For a 57600 baud rate, the sampling rate of the signal would therefore be => 16 x 57600 => 921600 samples per second, am i right?

Would i need to upsample this 921600s/S signal given that I would then need to multiply this signal by a carrier wave and then output it using a DAC (PMOD DA2) whose sampling rate is that of 1000000 samples per second?

 

[mrflibble]

To reduce confusion regarding the baud rate generator, read this one: https://www.fpga4fun.com/SerialInterface2.html

 

[std_match]

It is only the UART receiver that needs oversampling, so the data sampling can be done close to the middle of each bit.
16 times oversampling is standard but overkill in most cases. The UART's with 16 times oversampling ofthen take 3 samples at consecutive clock cycles in the middle of the bits and use the majority result to reduce the effect of glitches. The minimum integer oversampling factor that will work without problems is 3, but no majority vote is then possible

The UART transmitter doesn't need oversampling. It can have the clock equal to the baud rate.

No additional oversampling should be needed if you want to modulate a carrier, but I don't understand exactly what you are trying to do. You must transfer the data to the DAC clock domain, but for that you need a synchronizer, not oversampling.

 

[Christian Chetcuti]

You might have not understood me, I am sending ASCII characters from PC to fpga. The 8-bit received binary data from the PC is the signal which I thought i would need to up-sample.

How do i decide by what rate I would need to up-sample this received signal?

 

[std_match]

You might have not understood me, I am sending ASCII characters from PC to fpga. The 8-bit received binary data from the PC is the signal which I thought i would need to up-sample.

How do i decide by what rate I would need to up-sample this received signal?

Ok, so the DAC and "multiply this signal by a carrier wave" have been removed from the question?

To receive the data in the FPGA you need oversampling. The simplest is integer oversampling and 3 or any higher oversampling factor will work. It is not necessary to get the exact baudrate. The margin depends on the oversampling factor, but 1-2% off is acceptable in most cases.

The basic algorithm is:

1. Wait for the start bit leading edge (the '1' to '0' transition)
2. Wait for half a bit time (this is the main reason for needing oversampling)
3. Check the data bit again, if not '0' it was a false start bit
4. Wait one bit time
5. Sample one data bit
6. Goto step 4 until all data bits have been read
7 Wait one bit time
8 Sample the stop bit, if not '1' it is a framing error


To transmit data from the FPGA to the PC you don't need oversampling

 

[Christian Chetcuti]

Thanks for the reply std-match.

I have followed the method you mentioned for oversampling when designing the receiving part of the UART and have succeeded in obtaining the required data whenever I send a message (an ASCII character) from the PC to the FPGA.

Next up in my project is the modulation of this message and then conversion of the output signal from digital to analog through the use of a DAC.

Therefore the question is once I have received this message using UART, what would I need to do before multiplying this message with the carrier wave (100kHz wave) and then passing it to the DAC whose sampling rate is that of 1M samples/s ?

Ok, so the DAC and "multiply this signal by a carrier wave" have been removed from the question?

To receive the data in the FPGA you need oversampling. The simplest is integer oversampling and 3 or any higher oversampling factor will work. It is not necessary to get the exact baudrate. The margin depends on the oversampling factor, but 1-2% off is acceptable in most cases.

The basic algorithm is:

1. Wait for the start bit leading edge (the '1' to '0' transition)
2. Wait for half a bit time (this is the main reason for needing oversampling)
3. Check the data bit again, if not '0' it was a false start bit
4. Wait one bit time
5. Sample one data bit
6. Goto step 4 until all data bits have been read
7 Wait one bit time
8 Sample the stop bit, if not '1' it is a framing error


To transmit data from the FPGA to the PC you don't need oversampling

 

[std_match]

I don't understand what you want to do. When you have received the data with the UART you have it in parallel format. Now you want to use that data to modulate a carrier? Please specify the whole chain so we can understand what you are trying to do.

 

[Christian Chetcuti]

Yes exactly as you said std_match.

I am receiving data from UART and have it in parallel format. Now i want to use this data to modulate a carrier (generated using a DDS IP Core). The modulation output is then passed over to the DAC (whose sample rate is of 1Msps)

I don't understand what you want to do. When you have received the data with the UART you have it in parallel format. Now you want to use that data to modulate a carrier? Please specify the whole chain so we can understand what you are trying to do.

 

[std_match]

What are you modulating? Amplitude, phase, frequency?
The parallel data will remain unchanged until the next byte is received by the UART.
The baud rate will only determine the maximum change rate for the modulation.

What is the purpose of the modulated signal?

 

[Christian Chetcuti]

What are you modulating? Amplitude, phase, frequency?

I am modulating amplitude.

What is the purpose of the modulated signal?

The modulated signal will then be transmitted to a receiver

 

[std_match]

I am modulating amplitude.
The modulated signal will then be transmitted to a receiver

What is the actual information that you want to transfer to the receiver?
How will you use it to modulate the amplitude?
If it is the serial data sent to the UART that you want to transfer to the receiver, you have a problem.

Please describe how the receiver will extract the information from the modulated signal.