UPF in FPGA

[no_mad]

Hi guys,

Anyone have any experience enabling UPF in FPGA.
I have a lot of questions, so I would like to get some inputs and feedback.

Please help me out here.

Thanks!

 

[KlausST]

Hi,

Instead of asking whether a member has experience in topic xxx....it's better and faster to directly ask the question(s) you really want to know.

Give informations what you are after, what you are working with, why you come to your questions.
Often it's useful to refer to documents, give software names and versions, or to upload a (hand drawn) sketch.

Then ask max. 3 questions.

Klaus

 

[no_mad]

Noted.
Sorry, my bad.

Actually, I'm starting to work on FPGA prototyping with UPF.
I would like to understand how those power strategies, for example, isolation strategy, retention strategy, and power switch are implemented in FPGA and how do you verify those strategies in the FPGA platform.

In FPGA, I understand that FPGA is a single supply voltage.
1) how FPGA map or handle Power Switch and ack_port & control_port?
2) Do I need to make sure ack_port and control_port of Power Switch connected to its respective signal in design?
or bypass those signals in design?


I'm using HAPS-80 and HAPS-100.
Tools:
1) Simulation: VCS
2) Synthesis: Protocompiler
3) Timing closure: Vivado

Thanks!