Noted.
Sorry, my bad.
Actually, I'm starting to work on FPGA prototyping with UPF.
I would like to understand how those power strategies, for example, isolation strategy, retention strategy, and power switch are implemented in FPGA and how do you verify those strategies in the FPGA platform.
In FPGA, I understand that FPGA is a single supply voltage.
1) how FPGA map or handle Power Switch and ack_port & control_port?
2) Do I need to make sure ack_port and control_port of Power Switch connected to its respective signal in design?
or bypass those signals in design?
I'm using HAPS-80 and HAPS-100.
Tools:
1) Simulation: VCS
2) Synthesis: Protocompiler
3) Timing closure: Vivado
Thanks!