Up down counter ideas

[boots_n_braces]

Hi all,
Im a bit stuck on a current project I need an up down counter (pref 8 bit but 4 will suffice) but the up signal will be coming from one source and the down from another source (not synchronous to clock or each other) So i really need either an counter ic or discrete design for a counter with 2 seperate inputs for up and down as opposed to 1 input and an up/down select input. The signals will be up to but not beyond 500khz.

If anyone can help it would be greatly appreciated, Im off to trawl my logic books for a soloution

Thanks
harry

 

[HTA]

An up/down counter with Up/Down clock inputs is like the 74HCT193. But with two asynchronous clocks for up and down it is needed to synchronize them to avoid metastable conditions. Thus you have to synchronize both with a higher clockfrequency to avoid to get a up and down clock at the same time. Maybe this website will help in the design: https://www.electronics-tutorials.ws/logic/logic_1.html .

Enjoy your design work!

 

[boots_n_braces]

Apart from the clash if both inputs go high at once are there any other synchronization issues? clock pulses cant be synchronized due to timing nature of the system but depending on how the chip responds to both inputs going high at the same time a collision might be acceptable. If both went high at the same time would the count remain the same or would wierd and wonderfull things happen?

Thanks for the fast reply

 

[HTA]

Metastable means it is undefined what happens. If you know the maximum of incoming up/down clock frequency(and puls width) you can use two flipflop for each count channel. One use the negative edge to ysnchronize and the other the positive edge. The synchronization clock frequency should be high enough to meet the FF setup and hold times.

Enjoy your design work!

 

[boots_n_braces]

Brilliant a bit of playing on spice got it working thank you very much!!