vvsvv
Full Member level 1
unsigned so std_logic_vector
what is the diffierence between UNSIGNED AND STD_LOGIC_VECTOR?
when I program vhdl , I used std_logic_vector(18 downto 0), however , there is negtive NUBMER !! BUT ,what I want is the ADDRESS of Sram , that is to say , it should be positive NUMBER !!
MAY I change std_logic_vector to "unsigned "?
and by doing so , may i solve my probloem ?
thanks!
what's more , May I use unsigned( 18 downto 0) in my entity port declaring?
:wink:
what is the diffierence between UNSIGNED AND STD_LOGIC_VECTOR?
when I program vhdl , I used std_logic_vector(18 downto 0), however , there is negtive NUBMER !! BUT ,what I want is the ADDRESS of Sram , that is to say , it should be positive NUMBER !!
MAY I change std_logic_vector to "unsigned "?
and by doing so , may i solve my probloem ?
thanks!
what's more , May I use unsigned( 18 downto 0) in my entity port declaring?
:wink: