I might see the issue. There are two possibilities I see.
Firstly, the numbering scheme is weird for Xilinx devices. Needlessly weird really. The FPGA pin names are based on something relevant to Xilinx, but require a lookup table to determine the GT tile location for a given device. It is possible you've managed to connect the wrong common tile to the wrong channel.
Second, there is clock chaining that may be required. The Kintex allows the reference clock to be sourced from other tiles that are near enough. I'm not sure if the tools can pick this up. You may need to place the other gtx common tiles in an appropriate mode. eg, muxes set to pass through, pll powered down, io buffer powered down, etc... This gets the clock to the correct clock region.