[SOLVED] Unknown in Equality Operand during RTL Simulation

[YuLongHuang]

HI~!

I'd like to make sure one thing and listen what you have thought.
What would happened if unknown is shown in equality operand during RTL simulation ?

for example, what happened to r if a, b, c become unknown in following description ?
always @ ( posedge clk or posedge rst )
if ( rst )
r <= 0;
else
if ( a == 0 | b == 0 )
r <= 1;
else if ( c == 1 )
r <= 1;

According to my simulator, the result is that r will keeps the same value as last clock edge.
More specifically, the if ( ...... ) will be skipped if the operand is unknown.

Therefore, if a, b, c become unknown, r will hold the previous value instead of becoming unknown.
This behavior is inconsistent with the result of post-layout simulation.
There is no such problem since it's netlist during post-sim.

How do you think about ?
Of course it's more related to how Verilog standard is defined.

 

[YuLongHuang]

Hi,

I think this is simulator specific. Because in some of the simulator if we are checking the unknown value it will treat as logic 0, and performs accordingly. But some of them treated it as unknown itself.

I agree with you.
I have referred to specification of Verilog 1995 and 2001.
Both of them states that either of operand is unknown, the result will be unknown.
However, the result is not consistent when executing with NC-Verilog.
Maybe we can try this on different simulators.

 

[dave_59]

This is not simulator specific. This is what the standard says. (And you should get a copy of the latest 2012 standard for free)

The standard is X-optimistic when executing procedural statements (if, case, for, while, etc.), assuming an unknown will take the false branch. So even though the result of the equality operator is unknown, the if-statement will take the false path.

The standard is X-pessimistic when evaluating expressions, there is only one representation of an unknown. If the same unknown fans out to different logic, then re-converges to the same logic, there is no way to know that you are dealing with the "same" unknown. For example:

reg A, B, C;
...
A = 1'bx;
B = A; // there could be many more levels of logic here
C = A && B || ! A && ! B;

C will be 1'bx even though we know it real hardware it must be 1. You need another tool besides a simulator to analyze the logic formally.

You can search for X-pessimism and X-optimism along with simulation versus synthesis mismatches to find a lot more information on this.

 

[YuLongHuang]

You can search for X-pessimism and X-optimism along with simulation versus synthesis mismatches to find a lot more information on this.

Awesome of you!
Very thankful of you, I have never heard these two words before.
Originally I just want to check out why post-sim is inconsistent with RTL simulation even though signoff pass.
With your help, it indicates that there can be unnecessary bugs in RTL.

I have searched for the key words you provided and found some articles discussing this.
The article is very clear and valuable to read.
I will research these articles later and post a new thread if there is more question.

Thanks for the help above.
Polo :grin: