unknown Error in VHDL

[Jaffry]

Hi all,

I have an unknown and irritating error in VHDL, I have declared my signals as std_logic, but I recieve the following error for my case strucure. (I have put both error and code snippet below)

Line 128: Type std_logic does not match with the integer literal

architecure behavahioral of data_ent is 
...
signal sel_f, sel_opath : std_logic_vector(1 downto 0);
signal wr_enf0, wr_enf1, wr_enf2, wr_enf3 : std_logic;
--wr_en is the input signal with type std_logic
...
begin
...
process(sel_f,wr_en)
begin

case sel_f is
when "00" => wr_enf0 <= wr_en; wr_enf1 <= '0'; wr_enf2 <= 0; wr_enf3 <= 0;
when "01" => wr_enf1 <= wr_en; wr_enf0 <= '0'; wr_enf2 <= 0; wr_enf3 <= 0;
when "10" => wr_enf2 <= wr_en; wr_enf0 <= '0'; wr_enf1 <= 0; wr_enf3 <= 0;
when "11" => wr_enf3 <= wr_en; wr_enf0 <= '0'; wr_enf2 <= 0; wr_enf1 <= 0;
when others => wr_enf0 <= '0'; wr_enf1 <= '0'; wr_enf2 <= 0; wr_enf3 <= 0;
end case;

end process;

Please suggest what is wrong. What does it means by integer literal.

bests,
Jaffry

 

[permute]

literal -- a hard-coded value with no other name. (eg, not a named constant or generic but rather something like "0100111")

your issue is that 0 is an integer value, "0" is a std_logic_vector, and '0' is a std_logic. you used 0 when you should have used '0'.

 

[syedshan]

Yes it is a silly mistake which took almost half of my day trying and trying to rectifiy, later I saw that I just did not put single quotes with zeros...'0'

Thank you again

Jaffry

 

[Jackwin]

wr_enf1<='0';wr_enf2<='0';wr_enf3<='0', because they are std_logic and you should be careful!

Good luck!