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unity gain buffer topologies

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jiesteve

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Could someone please send me pointers to good references on unity-gain buffer amps? I need to drive ~5pF capacitive load in ~15ns.
 

sethtalk

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what's range for vdd?CMR? power consumption?
output range?
you must have thease spec and then choose
suitable opamp topology,do some op research,
may be you will find answer in general textbooks!
 

    jiesteve

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jiesteve

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VDD is 1.6 - 2.0, nominal is 1.8V
Input/Output CMR is 0.8 - 1.3V
Output load is 5pF
Current consumption target < 1mA
Settling time ~ 15ns

I'm looking into class AB output stages for low-quiescent current when the input is steady...

any suggestions for topologies are appreciated...

thanks!
 

sethtalk

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1.6v vdd+0.5v cmr --> i suggest the two stage ota is appropriate one ,
if you also need high gain , choose folded cascode as first stage,
and hybrid cascode compensation
but, quiscient curret consumes 1mA should not be achived easily,
i have designed a fully diff. ota with 2pF,15ns settling ota before (first stage is folded cascode),
it consume more than 2mA
 

    jiesteve

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rainman.cn

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hi, sethtalk, can you tell me which tools you use to draw the sch? its very good.
 

jiesteve

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Ok I'm seeing a problem with the CMR requirement... I think I need a N+P input pair... I don't need much gain.. Is there a way to do the N+P input pair w/o having to cascode the 2nd stage?

vt is also killing me on the process...it's about 0.65v...ridiculous...
 

sethtalk

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rainman.cn,
i use microsoft viso 2003 to plot the schematic,
i put the schematic model in EDAboard



Added after 1 hours 34 minutes:

Added after 53 seconds:

jiesteve,
yu can ref to the paper, it proposed 1.8v op with class-ab i/o stage

"Compact low-voltage power-efficient operational amplifier cells for VLSI"
 

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