RM92
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Hi,
I have just started VHDL coding and am trying to use FreeHDL for analysis and simulation.
"syntax error, unexpected t_SIGNAL, expecting t_END at signal"
shown when trying to do component instantiation to make a 4-i/p AND from 3 2-i/p ANDs.
error is shown on the line where i have declared the signals.
any idea what may be the problem?
I have just started VHDL coding and am trying to use FreeHDL for analysis and simulation.
"syntax error, unexpected t_SIGNAL, expecting t_END at signal"
shown when trying to do component instantiation to make a 4-i/p AND from 3 2-i/p ANDs.
error is shown on the line where i have declared the signals.
any idea what may be the problem?
