promach
Advanced Member level 4
I have some questions about http://fpgacpu.ca/fpga/Pipeline_Skid_Buffer.html
1) Why is skid buffer designed to be 2-entries FIFO instead of just 1-entry FIFO ?
2) Quoted from the article , why two cycles to start, and two cycles to stop ?
1) Why is skid buffer designed to be 2-entries FIFO instead of just 1-entry FIFO ?
However, pipelining handshaking is more complicated: simply adding a pipeline register to the valid, ready, and data lines will work, but now each transfer take two cycles to start, and two cycles to stop.
2) Quoted from the article , why two cycles to start, and two cycles to stop ?