understanding JFET fixed bias method

[fm101]

Hi,
I have the following 2N5459 JFET fixed biased circuit in proteus as shown below. I calculated drain current Id and drain voltage Vd but the circuit simulation does not show the expected values. I am not sure whether my calculation is correct or it is proteus.
I took Vgs(off)=Vp=-2V with Idss=4mA which are minimum values from 2N5459 datasheet. With applied Vgs=-1V, Vdd=5V and using transconductance equation Id=Idss(1-Vgs/Vp)^2 gives Id=1mA and with Vd=Vdd-Id*Rd gives Vd=5V-(1mA)(1kOhm)=4V but the simulation shows Id=0 and Vd=5V.

Is this not the way to bias JFET?

 

[KlausST]

Hi,

I took Vgs(off)=Vp=-2V with Idss=4mA which are minimum values from 2N5459 datasheet.

I can`t find this information in the Fairchild datasheet.
Maybe you use a different one. I don´t know.

Klaus

 

[fm101]

Hi,


I can`t find this information in the Fairchild datasheet.
Maybe you use a different one. I don´t know.

Klaus

hi please see https://www.mit.edu/~6.301/2N5459.pdf

 

[KlausST]

Hi,

And where did you find your values?

Klaus

 

[fm101]

Hi,

And where did you find your values?

Klaus

if I am not mistaking, the values I used is indicated below

 

[KlausST]

Hi,

Don´t mix both lines.

One tells V_GS_off -2V, but not at V_DS=5V and not at I_D= 4mA
The other tells -4mA, but not at V_GS=-1V and V_DS=15V.

V_GS_OFF is defined at 10nA. But your measurement device has a 0.00mA display, thus it´s resolution is 10uA which is 100 times 10nA

--> I recommend to do simualtions with exactly same parameters as the datasheet tells. Then you can verify whether the simulation matches the Fairchild datasheet or not.

Klaus

 

[fm101]

I have been looking around for some good worked out example for JFET biasing because most of these just simply specifies values for Idss and Vgs(off) and starts calculating Id and Vd using transconductance equation or graphical method. But suppose I want Id=5mA and Vd=2V with Vdd=5V what is the correct way to calculate the Rd and -Vgs required? Any tutorial link wold be helpful.

 

[Audioguru]

The voltage ranges are 4 to 1. Where can you find a Jfet that matches the voltage that your simulation uses?
You must add some negative feedback so that any passing 2N5459 works.

 

[FvM]

The obvious explanation is that Proteus doesn't provide a correct JFET model, respectively not typical 2N5459 parameters as other simulators do. Nevertheless I agree with Audioguru that a useful circuit should account for the expectable Vp and Idss variations of real parts. According to datasheet, there should be nonzero drain current with Vgs = -1V.

 

[KlausST]

Hi,

I doubt there is an exact way to calculate this, because this JEFT has a huge tolerance in V_GS to I_D.

Klaus

 

[danadakk]

Looks reasonable.

From attached model library.


Regards, Dana.

 

[crutschow]

The transconductance of a JFET is high, so any small change in the Vgs(off) value will cause a large change in the drain current.

 

[dick_freebird]

With that much slop in VP0 you may have some work
ahead of you in (re)fitting the FET model to act right.
I'd start with a Vds=15 DC gate sweep, like -10 to 0 by 0.1,
and see if the model returns JFET-like behavior at all
(never mind the values). Once you can see a "live"
3-terminal JFET you can worry about detail fitting.

Just because somebody gives you a model doesn't
mean (a) it works, (b) it works in the target simulator
what with dialect differences, (c) does so accurately.
Particularly LTSpice libraries in other simulators must
be inspected for whether they use Linear Tech's (now
ADI's) funky behavioral language rather than a more
standard compact model, and whether all of the little
details like CGS vs MKS units, defaults for params left
un-set in the model card, etc. are really 1:1 compatible.

 

[danadakk]

Transconductance -

BJT vs. FET Transistors

This article gives an overview of BJT vs FETs. It explains the advantages and disadvantages of both, as well as the difference in their usage.

www.learningaboutelectronics.com

Regards, Dana.

 

[fm101]

@Audioguru, how come the voltage range 1 to 4? I am using 2N5459 JFET and I am trying to bias the JFET with fixed bias method and negative bias has been applied via gate with separate source. Feedback is not used in fixed bias method(in self bias it is used).

@FvM, partly I agree because using a different JFET(2N5432) simulation I got some drain current and drain voltage for the same circuit but still the calculation does not give expected values.

@KlausST, exact solution not only for this JFET but there is no calculating method to give at least near expected value for drain current and drain voltage. I tried not only proteus but also multisim

@danadakk, your circuit shows positive bias on the gate

@dick_freebird, i understand model and simulator are not prefect, i performed simulation with other JFET model in proteus as well as in other simulation software multisim, there is no expected values, at least near expected values

what I am looking for is how to calculate the Vgs(off), Id and Vd to bias the JFET in fixed bias circuit(biasing in ohmic region).

thank you all

 

[FvM]

what I am looking for is how to calculate the Vgs(off), Id and Vd to bias the JFET in fixed bias circuit(biasing in ohmic region).

Due to parameter variation, fixed bias without DC feedback or individual adjustment isn't feasible.

 

[fm101]

does anybody know the equation for drain characteristics, that is equation relating Id and the Vds for given Vgs?

 

[danadakk]

@Audioguru, how come the voltage range 1 to 4? I am using 2N5459 JFET and I am trying to bias the JFET with fixed bias method and negative bias has been applied via gate with separate source. Feedback is not used in fixed bias method(in self bias it is used).

@FvM, partly I agree because using a different JFET(2N5432) simulation I got some drain current and drain voltage for the same circuit but still the calculation does not give expected values.

@KlausST, exact solution not only for this JFET but there is no calculating method to give at least near expected value for drain current and drain voltage. I tried not only proteus but also multisim

@danadakk, your circuit shows positive bias on the gate

@dick_freebird, i understand model and simulator are not prefect, i performed simulation with other JFET model in proteus as well as in other simulation software multisim, there is no expected values, at least near expected values

what I am looking for is how to calculate the Vgs(off), Id and Vd to bias the JFET in fixed bias circuit(biasing in ohmic region).

thank you all

Look at sweep of gate, its from 0 to - 1 V.

Regards, Dana.

 

[KlausST]

Hi

does anybody know the equation for drain characteristics, that is equation relating Id and the Vds for given Vgs?

No. I don´t.

Maybe you don´t understand the problem here. I try to explain as an example.
Let´s say you have several 2N5459 JFETs.
You build a circuit and find out that with V_GS of -2.1V you get I_D = 5mA @ V_DS = 5V.

Now just replace the JFET with another 2N5459. Same V_GS, same V_DS.
and you will see that the I_D isn´t 5mA anymore. It may be about zero, it may be about 10mA.. or anything inbetween. Unknown.
--> impossible to calculate.

***
So the 2N5459 is not suitable for your application.
But maybe there are other JFETs - with more tightly tolerated specifications - possible to use for this application.

Klaus

 

[FvM]

does anybody know the equation for drain characteristics, that is equation relating Id and the Vds for given Vgs?

Ideal quadratic FET characteristic has zero output conductance in saturation region, real FET has small output conductance.

See semiconductor device textbooks, or e.g. the below Siliconix Application Note