I was trying to compile my design into MAX10 FPGA 144 QFP Package(Device: 10M02). My IO's are 95 (out of 101). Quartus tool while fitting gives the following error messages
Error (176205): Can't place 93 pins with 3.3-V LVCMOS I/O standard because Fitter has only 91 such free pins available for general purpose I/O placement
If I let the quartus to choose the IO voltage levels, it selects 2.5V and device fitting is successful. Can anybody explain the error as I require all the IOs to be 3.3V
You should be able to answer the question yourself, if you check which pins don't accept 3.3V VCCIO. I guess, you have fixed configuration voltage to 2.5V which constrains the respective bank.
so either use 3.3V as configuration voltage or just add some logic level converters.
.. either for the configuration signals or the couple signals that are on the 2.5V bank.
You get it by reading the documentation for the MAX10 part you are using. The documentation will tell you how many pins support 3.3V and what restrictions there are about where these pins are.
Usually if you have some pins that don't have to be high speed you could just move those to 2.5V I/O through voltage translators.
try with 91 pins.
The compiler will then use all pins available for use with 3V3.
Now check which (2) pins it does not use. Tell us. Or check the alternative use of these remaining pins on your own.
Without JTAG pin sharing, dedicated JTAG pins are substracted from available GPIO count
Error (176205): Can't place 100 pins with 3.3-V LVCMOS I/O standard because Fitter has only 97 such free pins available for general purpose I/O placement
Error (176204): Can't place pins due to device constraints
Hi FvM
Yes, it works. But I do not understand why JTAG should be used as general purpose IO. I want to use this as dedicated JTAG port. Where do we find the reference. Please clarify