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Understanding DDR3 DRAM configuration

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shaiko

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Hello,

I'm trying to learn about the various configuration options of DDR3 memory.
For example, please review the following document:

https://www.ti.com/lit/an/sprabi1b/sprabi1b.pdf

At Page 11, Table 2, Row 2 - you see this:
1Gb / (8M × 16 × 8) × 2 SDRAMs

This is how I understand it:

1Gb - Is the total capacity of the DRAM chip.

8M - Is the size of every memory sub-array. It is organized internally into rows and columns (CAS/RAS) when every row/column intersection addresses only a single bit per sub-array.

16 - Is the width of the input/output data of the chip. A single bit comes from every memory sub-array and concatenated to the total width. Therefore, the width exactly matches the number of memory sub-arrays per bank.

8 - Is the number of banks per dram chip.

Is my observation correct?
 
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shaiko

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How are different banks accessed on the same DRAM chip?
Does every bank have a different offset row address?
 

shaiko

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Thanks for your help.
This is one of the (many) documents I've stumbled upon before posting.
It has good information about timing, but doesn't discuss memory configuration in detail.
 

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