shaiko
Advanced Member level 5
Hello,
I'm trying to learn about the various configuration options of DDR3 memory.
For example, please review the following document:
**broken link removed**
At Page 11, Table 2, Row 2 - you see this:
1Gb / (8M × 16 × 8) × 2 SDRAMs
This is how I understand it:
1Gb - Is the total capacity of the DRAM chip.
8M - Is the size of every memory sub-array. It is organized internally into rows and columns (CAS/RAS) when every row/column intersection addresses only a single bit per sub-array.
16 - Is the width of the input/output data of the chip. A single bit comes from every memory sub-array and concatenated to the total width. Therefore, the width exactly matches the number of memory sub-arrays per bank.
8 - Is the number of banks per dram chip.
Is my observation correct?
I'm trying to learn about the various configuration options of DDR3 memory.
For example, please review the following document:
**broken link removed**
At Page 11, Table 2, Row 2 - you see this:
1Gb / (8M × 16 × 8) × 2 SDRAMs
This is how I understand it:
1Gb - Is the total capacity of the DRAM chip.
8M - Is the size of every memory sub-array. It is organized internally into rows and columns (CAS/RAS) when every row/column intersection addresses only a single bit per sub-array.
16 - Is the width of the input/output data of the chip. A single bit comes from every memory sub-array and concatenated to the total width. Therefore, the width exactly matches the number of memory sub-arrays per bank.
8 - Is the number of banks per dram chip.
Is my observation correct?
Last edited:
