pcrider said:Thanks for the replies and the links.
I finally got the data sheet for the 5500. Now I have a couple new questions. The data sheet says:
The STi5500 has a 32-bit signed (twos complement) address space where the address ranges from MinInt (#80000000) at the bottom to MaxInt (#7FFFFFFF) at the top. 32-bit (four-byte) words are addressed by 30-bit word addresses, and a 2-bit byte-selector identifies the bytes in the word.
Memory is divided into areas with different memory characteristics and intended purposes. Some areas are dedicated to a specific purpose either because they contain memory-mapped devices or because they are reserved by the system.
external memory addressing (EMI) is from
#40000000-#4FFFFFFF
#50000000-#5FFFFFFF
#60000000-#6FFFFFFF
#70000000-#7FFFFFFD
from there boot entry byte0 is 7FFFFFFE
and boot entry byte1 is #7FFFFFFF
When I put these numbers into a calculator each area is FFFFFFF this is
268435455 in decimal. That doesn't make any sense to me. I realise it memory addressing not actual memory, but the numbers still seem strange. Can someone explain this addressing to me?
Thanks Mike B. aka PcRider
tanuki said:Try the STi5518 datasheet, it's more clear on the memory space. The memory space description starts from zero.
Datasheets and reference code can be found at
h**p://dvb-upload.com/
8.1.4 Boot ROM
When the processor boots from ROM, it jumps to a boot program held in ROM with an entry point 2 bytes from the top of memory at #7FFFFFFE. These 2 bytes are used to encode a negative jump of up to 256 bytes down in the ROM program. For large ROM programs it may then be necessary to encode a longer negative jump to reach the start of the routine.
tanuki said:The critical details you're missing is the flash memory address space decoder circuit. It's most likely a PAL/GAL type device that logically AND's the higher order STi5500 address lines to create the OE# signal (and possilbly others signals too). These extra circuits are shown only on the Pansat 300A schematics.
From the STi datasheet:
8.1.4 Boot ROM
When the processor boots from ROM, it jumps to a boot program held in ROM with an entry point 2 bytes from the top of memory at #7FFFFFFE. These 2 bytes are used to encode a negative jump of up to 256 bytes down in the ROM program. For large ROM programs it may then be necessary to encode a longer negative jump to reach the start of the routine.
The flash memory is decoded such that the last Flash Memory address (#3FFFFF or #7FFFFF) aligns with the top of the STi5500 memory address (#7FFFFFFF). The STi5500 begins execution using the last two bytes as a pointer
Assuming the decoder enables the entire flash memory as only one segment.
Start of Flash memory address in STi5500 address space:
Case 1: 4 Megabyte flash: #7FFFFFFF - #3FFFFF = #7FC00000
Case 2: 8 Megabyte flash: #7FFFFFFF - #7FFFFF = #7F800000
tanuki said:The critical details you're missing is the flash memory address space decoder circuit. It's most likely a PAL/GAL type device that logically AND's the higher order STi5500 address lines to create the OE# signal (and possilbly others signals too). These extra circuits are shown only on the Pansat 300A schematics.
From the STi datasheet:
8.1.4 Boot ROM
When the processor boots from ROM, it jumps to a boot program held in ROM with an entry point 2 bytes from the top of memory at #7FFFFFFE. These 2 bytes are used to encode a negative jump of up to 256 bytes down in the ROM program. For large ROM programs it may then be necessary to encode a longer negative jump to reach the start of the routine.
The flash memory is decoded such that the last Flash Memory address (#3FFFFF or #7FFFFF) aligns with the top of the STi5500 memory address (#7FFFFFFF). The STi5500 begins execution using the last two bytes as a pointer
Assuming the decoder enables the entire flash memory as only one segment.
Start of Flash memory address in STi5500 address space:
Case 1: 4 Megabyte flash: #7FFFFFFF - #3FFFFF = #7FC00000
Case 2: 8 Megabyte flash: #7FFFFFFF - #7FFFFF = #7F800000
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