Unbuffered cells have lower and more asymmetric drive
strength ("buffered" merely means the output is a regular
inverter or series pair, sinbgle-stack while (say) a nand4
would have a 4-high NMOS output stack and 4 parallel
PMOS, so expect HL drive strength to be low and loading
sensitivity of that transition, high).
If you've got a ton of slack or a known-light and close-haul
load then unbuffered.
There should be a point where the buffered and unbuffered
show equal delays (@ center PVT, or @ WC - the latter
being what you'd probably design to) and knowing that
"crossover point" might let you make off-the-cuff decisions
about what type to start with.
But libraries may also make that decision for you; I have
seen cases where, for example, nand2 is unbuffered but
nand3 and nand4 are buffered (for the stack-height
concern).