Unable to view Inernal Signal in gHDL ghw native format

[promach]

I could not view the internal signal even though I am using the formal format *ghw

Any advice on what is wrong with how I stitch together all three vhd source files ?

Source code:

​

View attachment key_expansion.zip

GTKwave:

​

 

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You have multiple architectures with the entity called key_expansion being used. Your code only has the round_constant.vhd code compiled and simulating depending on the compile order.

After you fix that you'll have a bunch of errors (x's) all over your simulation.

Next time put the code within syntax or code tags instead of uploading a zip file. I was almost not going to help because of this.

 

[promach]

I suppose an entity can have multiple architectures. How do I fix the multiple architectures issue ?

anything wrong with the compile order as in the makefile at https://paste2.org/Kv7vD8xL ?

What do you mean by "put the code within syntax or code tags" ?

 

[TrickyDicky]

I suppose an entity can have multiple architectures. How do I fix the multiple architectures issue ?

Only use 1 architecture per entity, and put it in the same file.

What do you mean by "put the code within syntax or code tags" ?

There is a CODE button above the text box with a # on it. Otherwise you can wrap code inside \

[\code] (remove the first \ )or even better, use syntax instead as it adds syntax highlighting \[syntax=vhdl][\syntax]

[code]
-- this is a code tag
process(clk)
begin
  if rising_edge(clk) then
    a <= b;
  end if;
end process;

---

Code VHDL - [expand]
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--this is a syntax tag with nice colours
process(clk)
begin
  if rising_edge(clk) then
    a <= b;
  end if;
end process;

---

 

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Arrgh! This has nothing to do with multiple architectures.

You have a typo and are using the wrong entity name in the round_constant.vhd file's architecture line. This is a really stupid cut and paste error. It is real easy to find because your design with hierarchical structure shows up in simulation with only a single level.

Took me less than a minute to find the problem, once I loaded it into the simulator (didn't catch it during visual code inspection).

 

[promach]

Arrgh! This has nothing to do with multiple architectures.

You have a typo and are using the wrong entity name in the round_constant.vhd file's architecture line. This is a really stupid cut and paste error. It is real easy to find because your design with hierarchical structure shows up in simulation with only a single level.

Took me less than a minute to find the problem, once I loaded it into the simulator (didn't catch it during visual code inspection).

Thanks for your help. I have tried to solve another problem that pops up after that.



I have tried changing the initial value of rcon[31:0] by putting it outside of the clocked process (round_constant.vhd)

[SYNTAX=VHDL]architecture EXAMPLE of round_constant is

signal rcnt_next, rcnt: integer := 0;

begin

rcon <= x"00_00_00_00";

process(clk)
begin

if rising_edge(clk) then
	if(key_load = '1') then	
		rcnt <= 0;
	else		
		rcnt <= rcnt_next;
	end if;
end if;
end process;

[/SYNTAX]

However, I still have the red X simulation error.
What is the root cause ?

 

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Next time post the entire file. Having the statement rcon <= x"00_00_00_00"; shows nothing. The problem is due to some other line of code forcing one or more bits between [27:24] to be 1 when you have the assignment to rcon being 0. This is a typical problem with assigning a signal in multiple places in code. I always assign signals in a single process or only in one assignment statement.

Looking at your original code I'm not sure you understand how to write code that represents the hardware. You seem to be just writing code to program something that sort of does what you think you want to do instead.

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Code VHDL - [expand]
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architecture EXAMPLE of round_constant is
 
signal rcnt_next, rcnt: integer := 0;
signal rcon_int : std_logic_vector(31 downto 0) := (OTHERS => '0');
 
begin
 
  rcon <= rcon_int;
 
process(clk)
begin
 
if rising_edge(clk) then
    if(key_load = '1') then 
        rcon_int <= x"01000000";  -- trying to say rcon_int is a FF with key_load enable
        rcnt <= 0;
    else        
        rcnt <= rcnt_next;
    end if;
end if;
end process;
 
rcnt_next <= rcnt + 1;
 
 
process(rcnt_next)
begin
    
    case(rcnt_next) is
       when 0 => rcon_int <= x"01_00_00_00";  -- assigning rcon_int using a combinational circuit
       when 1 => rcon_int <= x"02_00_00_00";
       when 2 => rcon_int <= x"04_00_00_00";
       when 3 => rcon_int <= x"08_00_00_00";
       when 4 => rcon_int <= x"10_00_00_00";
       when 5 => rcon_int <= x"20_00_00_00";
       when 6 => rcon_int <= x"40_00_00_00";
       when 7 => rcon_int <= x"80_00_00_00";
       when 8 => rcon_int <= x"1b_00_00_00";
       when 9 => rcon_int <= x"36_00_00_00";
       when OTHERS => rcon_int <= x"00_00_00_00";
    end case;
 
end process;
 
end architecture EXAMPLE;

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so is rcon_int supposed to be a FF or a combinational circuit? Seems like you don't know, so how is the simulator supposed to know? Of course it ends up X as only bits that match will result in bits that show up a non-X.