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Unable to read wr_en, fifo_in using instantiation

aruna siddappa

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[Please use code or syntax tags for posted code]

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// fifo to read 32 bit data if wr_en=1
module fifo(
    input clk,
    input rst,
    input wr_en,
    input [31:0] fifo_in,
    output [31:0] fifo_out);
 
reg [31:0] reg_fifo;
 
//fifo instantiation with converter module
converter_8_32 fifo_dut(.clk(clk),.rst(rst),.valid_q(wr_en),.data_out(fifo_in));
 
always @(*) begin
    if(!rst) begin
        reg_fifo<=0; end
        else if (wr_en==1'b1) begin
            reg_fifo<=fifo_in; end
        else reg_fifo<=0;    
end
assign fifo_out=reg_fifo;
endmodule
 
//converter block to convert 8 bit input to 32 bit output for every 4 clocks.
////output is valid if valid_q=1 where we receive 32 bit data out
 
module converter_8_32(
    input clk,
    input valid,
    input rst,
    output reg valid_q,
    input [7:0] data_in, //8 bit input
    output reg [31:0] data_out); //32 bit data out
 
reg [7:0] temp_reg [0:3];
 
integer N=4;
always @ (posedge clk or negedge rst) begin
    if (!rst) begin     
        data_out<=0;
        valid_q<=0;
            end
 
    else if (!valid) begin
            data_out<=0;
            valid_q<=0;
            N<=4;
                       end
               
    else begin            
        temp_reg[N-1]<=data_in;
        N=N-1;    
        if (N==0) 
        begin 
            valid_q<=1;
            N<=4;
            end
                else begin
                valid_q<=0;
                data_out<=data_in; end
            end
        end
                                            
 
always @ (posedge clk) begin
        if (N==0)
        // concatentaion operator to concatenate previous 3 data along
    // with preset data_in to generate 32 bit data
        data_out<={temp_reg[3],temp_reg[2],temp_reg[1],data_in};
            
end
 
endmodule
 
Need help on this.
I am unable to read (valid_q) output of converter into (wr_en) of fifo.
Getting dont cares"x" for wr_en & fifo_in[syntax]
[automerge]1716529491[/automerge]
Waveforms are attached for the same

 

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Last edited by a moderator:
You don't show the test bench or other module instantiating the shown modules. Can't see why wr_en and fifo_in are undefined.
 
Is there anything wrong with my instantiation.
8 to 32 bit converter is working fine.
input to fifo is read only when wr_en is high.
wr_en is connected to output signal of valid_q (when valid_q=1, conversion of 8 to 32 bit is done)
 

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`timescale 1ns/1ps
module fifo_tb();
reg clk_tb;
reg rst_tb;
reg valid_tb;
reg [7:0] data_in_tb;
wire valid_q_tb;
wire [31:0] data_out_tb;
 
reg wr_en_tb;
reg [31:0] fifo_in_tb;
wire [31:0] fifo_out_tb;
 
converter_8_32 dut_converter (.clk(clk_tb),.rst(rst_tb),.valid(valid_tb),.data_in(data_in_tb),.valid_q(valid_q_tb),.data_out(data_out_tb));
fifo dut_top (.clk(clk_tb),.rst(rst_tb),.wr_en(wr_en_tb),.fifo_in(fifo_in_tb),.fifo_out(fifo_out_tb));
 
always # 1 clk_tb=~clk_tb;
always #8 valid_tb=~valid_tb;
integer i;
 
initial begin
 clk_tb=0;
 rst_tb=0;
 valid_tb=1;
 data_in_tb=0;
 #2.5 rst_tb=1'b1; 
 //valid_tb=1'b1;
 #0.5;
 for (i=0;i<255;i=i+1) begin
     data_in_tb=i;
     #2;
 end
 
 
end
 
 
endmodule[syntax]
 
 
my testbench code

 
Last edited by a moderator:
wr_en_tb and fifo_in_tb are nowhere driven in your testbench.

Please take the time to add code tags to posted code for better readability, e.g. use "syntax highlighter" function.
 
The below instantiation is connecting "wr_en" to "valid_q" in module fifo @ line 12 of my source code
"fifo_in" is connected to "data_out" of converter

fifo reads 32 bit data only when wr_en=1
do we need to drive wr_en_tb and fifo_in_tb in test_bench again??
Already "valid_q" and "data_out" are generated using module converter_8_32

@ line12 of source code
converter_8_32 fifo_dut(.clk(clk),.rst(rst),.valid_q(wr_en),.data_out(fifo_in));
--- Updated ---

Please guide whats wrong, what changes i have to make
 
Last edited:
Please help with above issue
Unable to figure out whats wrong in code.

I need 32 bit "fifo_out" to receive 32 bit "data_out" which is the of converter module

converter_8_32 fifo_dut(.clk(clk),.rst(rst),.valid_q(wr_en),.data_out(fifo_in));

reg [31:0] reg_fifo;

always @(posedge clk or negedge rst) begin
if(!rst) begin
reg_fifo<=0; end
else if (wr_en==1'b1) begin
reg_fifo<=fifo_in; end
else reg_fifo<=0;
end
assign fifo_out=reg_fifo;
endmodule

"wr_en" should follow "valid_q" output of converter module
 

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