How can we answer this without seeing what you have done?Am I doing anything wrong
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vga_sync is
port(
clk, reset: in std_logic;
hsync, vsync: out std_logic;
video_on, p_tick: out std_logic;
pixel_x, pixel_y: out std_logic_vector (9 downto 0)
);
end vga_sync;
architecture arch of vga_sync is
-- VGA 640-by-480 sync parameters
constant HD: integer:=640; --horizontal display area
constant HF: integer:=16 ; --h. front porch
constant HB: integer:=48 ; --h. back porch
constant HR: integer:=96 ; --h. retrace
constant VD: integer:=480; --vertical display area
constant VF: integer:=10; --v. front porch
constant VB: integer:=33; --v. back porch
constant VR: integer:=2; --v. retrace
-- mod-2 counter
signal mod2_reg, mod2_next: std_logic;
-- sync counters
signal v_count_reg, v_count_next: unsigned(9 downto 0);
signal h_count_reg, h_count_next: unsigned(9 downto 0);
-- output buffer
signal v_sync_reg, h_sync_reg: std_logic;
signal v_sync_next, h_sync_next: std_logic;
-- status signal
signal h_end, v_end, pixel_tick: std_logic;
begin
-- registers
process (clk,reset)
begin
if reset='1' then
mod2_reg <= '0';
v_count_reg <= (others=>'0');
h_count_reg <= (others=>'0');
v_sync_reg <= '0';
h_sync_reg <= '0';
elsif (clk'event and clk='1') then
mod2_reg <= mod2_next;
v_count_reg <= v_count_next;
h_count_reg <= h_count_next;
v_sync_reg <= v_sync_next;
h_sync_reg <= h_sync_next;
end if;
end process;
-- mod-2 circuit to generate 25 MHz enable tick
mod2_next <= not mod2_reg;
-- 25 MHz pixel tick
pixel_tick <= '1' when mod2_reg='1' else '0';
-- status
h_end <= -- end of horizontal counter
'1' when h_count_reg=(HD+HF+HB+HR-1) else --799
'0';
v_end <= -- end of vertical counter
'1' when v_count_reg=(VD+VF+VB+VR-1) else --524
'0';
-- mod-800 horizontal sync counter
process (h_count_reg,h_end,pixel_tick)
begin
if pixel_tick='1' then -- 25 MHz tick
if h_end='1' then
h_count_next <= (others=>'0');
else
h_count_next <= h_count_reg + 1;
end if;
else
h_count_next <= h_count_reg;
end if;
end process;
-- mod-525 vertical sync counter
process (v_count_reg,h_end,v_end,pixel_tick)
begin
if pixel_tick='1' and h_end='1' then
if (v_end='1') then
v_count_next <= (others=>'0');
else
v_count_next <= v_count_reg + 1;
end if;
else
v_count_next <= v_count_reg;
end if;
end process;
-- horizontal and vertical sync, buffered to avoid glitch
h_sync_next <=
'1' when (h_count_reg>=(HD+HF)) --656
and (h_count_reg<=(HD+HF+HR-1)) else --751
'0';
v_sync_next <=
'1' when (v_count_reg>=(VD+VF)) --490
and (v_count_reg<=(VD+VF+VR-1)) else --491
'0';
-- video on/off
video_on <=
'1' when (h_count_reg<HD) and (v_count_reg<VD) else
'0';
-- output signal
hsync <= h_sync_reg;
vsync <= v_sync_reg;
pixel_x <= std_logic_vector(h_count_reg);
pixel_y <= std_logic_vector(v_count_reg);
p_tick <= pixel_tick;
end arch;
library ieee;
use ieee.std_logic_1164.all;
entity vga_test is
port (
clk, reset: in std_logic;
sw: in std_logic_vector(2 downto 0);
hsync, vsync: out std_logic;
rgb: out std_logic_vector(2 downto 0)
);
end vga_test;
architecture arch of vga_test is
signal rgb_reg: std_logic_vector(2 downto 0);
signal video_on: std_logic;
begin
-- instantiate VGA sync circuit
vga_sync_unit: entity work.vga_sync
port map(clk=>clk, reset=>reset, hsync=>hsync,
vsync=>vsync, video_on=>video_on,
p_tick=>open, pixel_x=>open, pixel_y=>open);
-- rgb buffer
process (clk,reset)
begin
if reset='1' then
rgb_reg <= (others=>'0');
elsif (clk'event and clk='1') then
rgb_reg <= sw;
end if;
end process;
rgb <= rgb_reg when video_on='1' else "000";
end arch;
architecture arch of vga_sync is
-- VGA 640-by-480 sync parameters
constant HD : integer := 640; --horizontal display area
constant HF : integer := 16; --h. front porch
constant HB : integer := 48; --h. back porch
constant hr : integer := 96; --h. retrace
constant VD : integer := 480; --vertical display area
constant VF : integer := 10; --v. front porch
constant VB : integer := 33; --v. back porch
constant VR : integer := 2; --v. retrace
-- mod-2 counter
signal mod2_reg, mod2_next : std_logic;
-- sync counters
signal v_count_reg, v_count_next : unsigned(9 downto 0);
signal h_count_reg, h_count_next : unsigned(9 downto 0);
-- output buffer
signal v_sync_reg, h_sync_reg : std_logic;
signal v_sync_next, h_sync_next : std_logic;
[B] signal video_on_reg, video_on_next : std_logic;[/B]
-- status signal
signal h_end, v_end, pixel_tick : std_logic;
begin
-- registers
process (clk, reset)
begin
if reset = '1' then
mod2_reg <= '0';
v_count_reg <= (others => '0');
h_count_reg <= (others => '0');
v_sync_reg <= '0';
h_sync_reg <= '0';
[B]video_on_reg <= '0';[/B]
elsif (clk'event and clk = '1') then
mod2_reg <= mod2_next;
v_count_reg <= v_count_next;
h_count_reg <= h_count_next;
v_sync_reg <= v_sync_next;
h_sync_reg <= h_sync_next;
[B]video_on_reg <= video_on_next;[/B]
end if;
end process;
-- mod-2 circuit to generate 25 MHz enable tick
mod2_next <= not mod2_reg;
-- 25 MHz pixel tick
pixel_tick <= '1' when mod2_reg = '1' else '0';
-- status
h_end <= '1' when h_count_reg = (HD+HF+HB+hr-1) else --799
'0';
v_end <= '1' when v_count_reg = (VD+VF+VB+VR-1) else --524
'0';
-- mod-800 horizontal sync counter
process (h_count_reg, h_end, pixel_tick)
begin
if pixel_tick = '1' then -- 25 MHz tick
if h_end = '1' then
h_count_next <= (others => '0');
else
h_count_next <= h_count_reg + 1;
end if;
else
h_count_next <= h_count_reg;
end if;
end process;
-- mod-525 vertical sync counter
process (v_count_reg, h_end, v_end, pixel_tick)
begin
if pixel_tick = '1' and h_end = '1' then
if (v_end = '1') then
v_count_next <= (others => '0');
else
v_count_next <= v_count_reg + 1;
end if;
else
v_count_next <= v_count_reg;
end if;
end process;
-- horizontal and vertical sync, buffered to avoid glitch
h_sync_next <= '1' when (h_count_reg >= (HD+HF)) --656
and (h_count_reg <= (HD+HF+hr-1)) else --751
'0';
v_sync_next <= '1' when (v_count_reg >= (VD+VF)) --490
and (v_count_reg <= (VD+VF+VR-1)) else --491
'0';
[B] -- video on/off
video_on_next <= '1' when (h_count_reg < HD) and (v_count_reg < VD) else
'0';[/B]
-- output signal
hsync <= h_sync_reg;
vsync <= v_sync_reg;
[B] video_on <= video_on_reg;[/B]
pixel_x <= std_logic_vector(h_count_reg);
pixel_y <= std_logic_vector(v_count_reg);
p_tick <= pixel_tick;
end arch;
library ieee;
use ieee.std_logic_1164.all;
entity vga_test is
port (
clk, reset: in std_logic;
sw: in std_logic_vector(2 downto 0);
hsync, vsync: out std_logic;
rgb: out std_logic_vector(2 downto 0)
);
end vga_test;
architecture arch of vga_test is
signal rgb_reg: std_logic_vector(2 downto 0);
signal video_on: std_logic;
begin
-- instantiate VGA sync circuit
vga_sync_unit: entity work.vga_sync
port map(clk=>clk, reset=>reset, hsync=>hsync,
vsync=>vsync, video_on=>video_on,
p_tick=>open, pixel_x=>open, pixel_y=>open);
-- rgb buffer
process (clk,reset)
begin
if reset='1' then
rgb_reg <= (others=>'0');
elsif (clk'event and clk='1') then
rgb_reg <= sw;
end if;
end process;
rgb <= rgb_reg when video_on='1' else "000";
end arch;
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "clk" LOC = "p180" ;
NET "hsync" LOC = "p108" ;
NET "reset" LOC = "p101" ;
NET "rgb<0>" LOC = "p109" ;
NET "rgb<1>" LOC = "p111" ;
NET "rgb<2>" LOC = "p113" ;
NET "sw<0>" LOC = "p76" ;
NET "sw<1>" LOC = "p77" ;
NET "sw<2>" LOC = "p78" ;
NET "vsync" LOC = "p107" ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; ---------------------- entity vga640x480 is port ( clk,clr: in std_logic; --input 50 MHz clock and clear hsync: out std_logic; --horizontal sync pulse vsync: out std_logic; --vertical sync pulse rgb: out std_logic_vector(2 downto 0)-- red,green,blue ); end vga640x480; -------- architecture Behavioral of vga640x480 is constant hpixels: integer :=800; --nº pixeles horizontales (horizontal pixels) constant vlines: integer :=521; --nº de lineas horizontales (vertical lines) constant HFP: integer :=16; --horizontal front porch constant HBP: integer :=48; --horizontal back porch constant HSP: integer :=96; --horizontal sync pulse duration in pixels constant HVA: integer :=640;--horizontal visible area i.e. visible horizontal pixels per horizontal line constant VFP: integer :=10; --vertical front porch constant VBP: integer :=29; --vertical back porch constant VSP: integer :=2; --vertical sync pulse duration in pixels constant VVA: integer :=480;--vertical visible area signal hCounter,vCounter: unsigned(9 downto 0); --Contadores que llevan la cuenta de los pixeles en los que estoy signal displayON: std_logic;--activacion del display i.e. si se puede escribir pixeles o NO signal hEND : std_logic;--fin linea horizontal signal clk25: std_logic;--25 MHz clock begin --Clock frequency divider (PONERLO EN COMPONENTE SEPARADO) process(clk,clr) begin if clr ='1' then clk25 <='0'; elsif rising_edge(clk) then clk25 <= not clk25; end if; end process; --Contar pixeles horizontales process(clk25,clr) begin if clr='1' then hCounter <= (others => '0'); --parte asíncrona, reseteas contadores elsif (clk25'event and clk25 = '1') then --ver si clk_locked esta locked se ha incluido en el "clr" if hCounter=to_unsigned(hpixels-1,hCounter'length) then --has llegado al final de la linea horizontal hCounter <= (others => '0') ; --reset contador hEND <='1'; else hCounter <= hCounter+1; --incrementas contador hEND <='0'; end if; end if; end process; --Contar lineas horizontales dibujadas process(clk25,clr) begin if clr='1' then vCounter <= (others => '0'); elsif (clk25'event and clk25 = '1' and hEND = '1') then if vCounter=to_unsigned(vlines-1,vCounter'length) then --has dibujado la ultima linea horizontal vCounter <= (others => '0');--reset contador vertical else vCounter <= vCounter+1; -- incremento contador de lineas dibujadas en horizontal end if; end if; end process; hsync <= '0' when ((hCounter >= HVA+HBP) and (hCounter < HVA+HBP+HSP)) else '1' ; --lo pones a 0 cuando contador horizontal está entre 0 y 95 vsync <= '0' when ((vCounter >= VVA+VBP) and (vCounter < VVA+VBP+VSP)) else '1' ; -- lo pones a 0 cuando contador vertical está entre 0 y 1 --Condicion de que se pueda dibujar pixeles en el display (pantalla) displayON <= '1' when ((hCounter < HVA) and (vCounter < VVA)) else '0'; rgb <= "100" when displayON='1' else "000"; end Behavioral;
Then it is not working as it should. The code I showed must make the entire screen red, not just a line.Presently I am getting only a thin line fading downwards upto a few inches.
Code VHDL - [expand] 1 rgb <= "111" when displayON='1' and hCounter=xx and vCounter=yy else "000";
I was referring to the code in post #10. If you were referring to the same, pls. indicate the line number(s). I could not find pix_tick enable signal in the code.The pix_tick enable signals should be deleted as well.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity vga_sync is port( clk, reset : in std_logic; hsync, vsync : out std_logic; video_on, p_tick : out std_logic; pixel_x, pixel_y : out std_logic_vector (9 downto 0) ); end vga_sync; architecture arch of vga_sync is -- VGA 640-by-480 sync parameters constant HD : integer := 640; --horizontal display area constant HF : integer := 16; --h. front porch constant HB : integer := 48; --h. back porch constant hr : integer := 96; --h. retrace constant VD : integer := 480; --vertical display area constant VF : integer := 10; --v. front porch constant VB : integer := 33; --v. back porch constant VR : integer := 2; --v. retrace -- sync counters signal v_count_reg, v_count_next : unsigned(9 downto 0); signal h_count_reg, h_count_next : unsigned(9 downto 0); -- output buffer signal v_sync_reg, h_sync_reg : std_logic; signal v_sync_next, h_sync_next : std_logic; signal video_on_reg, video_on_next : std_logic; -- status signal signal h_end, v_end : std_logic; begin -- registers process (clk, reset) begin if reset = '1' then v_count_reg <= (others => '0'); h_count_reg <= (others => '0'); v_sync_reg <= '0'; h_sync_reg <= '0'; video_on_reg <= '0'; elsif (clk'event and clk = '1') then v_count_reg <= v_count_next; h_count_reg <= h_count_next; v_sync_reg <= v_sync_next; h_sync_reg <= h_sync_next; video_on_reg <= video_on_next; end if; end process; -- status h_end <= '1' when h_count_reg = (HD+HF+HB+hr-1) else --799 '0'; v_end <= '1' when v_count_reg = (VD+VF+VB+VR-1) else --524 '0'; -- mod-800 horizontal sync counter process (h_count_reg, h_end) begin if h_end = '1' then h_count_next <= (others => '0'); else h_count_next <= h_count_reg + 1; end if; end process; -- mod-525 vertical sync counter process (v_count_reg, h_end, v_end) begin if h_end = '1' then if (v_end = '1') then v_count_next <= (others => '0'); else v_count_next <= v_count_reg + 1; end if; else v_count_next <= v_count_reg; end if; end process; -- horizontal and vertical sync, buffered to avoid glitch h_sync_next <= '1' when (h_count_reg >= (HD+HF)) --656 and (h_count_reg <= (HD+HF+hr-1)) else --751 '0'; v_sync_next <= '1' when (v_count_reg >= (VD+VF)) --490 and (v_count_reg <= (VD+VF+VR-1)) else --491 '0'; -- video on/off video_on_next <= '1' when (h_count_reg < HD) and (v_count_reg < VD) else '0'; -- output signal hsync <= h_sync_reg; vsync <= v_sync_reg; video_on <= video_on_reg; pixel_x <= std_logic_vector(h_count_reg); pixel_y <= std_logic_vector(v_count_reg); p_tick <= clk; end arch;
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