Unable to get desired output of this neuromorphic circuit

[nikhadelokesh]

Hello everyone,

I am unable to get the desired output for the circuit attached with this post. I am trying to simulate this circuit on cadence with 180nm technology. This is a neuromorphic circuit which should produce spikes at the output. kindly give the suggestions.

 

[erikl]

What's the input?

 

[nikhadelokesh]

What's the input?

The input given is a constant current of 1nA.

 

[erikl]

I think it won't be easy to get this circuit to work. It depends rather sensibly on the threshold voltages of your process. And you'd have to adapt the individual W/L ratios to your technology - it probably won't work with the given - all the same - W/L ratios. This means you'll have to change and simulate a lot.

 

[erikl]

I think it won't be easy to get this circuit to work. It depends rather sensibly on the threshold voltages of your process. And you'd have to adapt the individual W/L ratios to your technology - it probably won't work with the given - all the same - W/L ratios.

Sorry, I was wrong here: As this is a regeneration circuit (positive and negative feedBack), it is possible to get it working anyway with the given W/L ratio for all transistors, which surely are not ideal for your intended process (and the circuit function probably still depends on the threshold voltages of the process).

I tried it with the threshold voltages of our former 0.18µm process (s. schematic below) and could get it to work with two schematic changes:
1. self supply of T7's gate bias
2. an essential change of the negative feedBack: R1 - C2

... and 2 changes in the standard parameter setting for the transient simulation:
1. Integration Method
2. reltol value

See here:

 

[nikhadelokesh]

Thank u very much sir. Your reply would really help me a lot.

I have few queries about the reply.
1. How to change the threshold of a transistor, kp, lambda in cadence?
2. what is reltol?

I am struggling with one more circuit. The circuit is originally designed in 0.36um technology. The circuit is a modified version the circuit for which you have helped me(i.e axon hillock circuit). The circuit is attached below.

 

[erikl]

1. How to change the threshold of a transistor, kp, lambda in cadence?

You can't change these values. They are fixed with an individual production process.

2. what is reltol?

relative error tolerance, a simulation control parameter which you can set in your simulation control file.

I am struggling with one more circuit. The circuit is originally designed in 0.36um technology. The circuit is a modified version the circuit for which you have helped me(i.e axon hillock circuit). The circuit is attached below.
View attachment 90750

What - exactly - is your struggling problem?

 

[nikhadelokesh]

What - exactly - is your struggling problem?[/QUOTE]

Actually the expected output is again spike. My problem is what should be the W/L ratio of each transistor? The paper in which this circuit is given the values of different parameter like Vadap, Vsf, Vrfr, Vlk are not given. what values of these parameters will give me desired result?

If you can give me your email id i will send the paper to you.

 

[erikl]

To get this task done, you must understand the circuit and how it works. For this, you need a thorough comprehension of analog circuit design, which will allow you to find estimated W/L values for your design. Then you will have to simulate the design and change device values (and possibly the design itself) often within several try-and-error loops until you get the expected and correct output. Besides a thorough knowledge of analog circuit design you need at least a basic understanding of the simulation tool which allows you to analyze your circuit (and which often can present results not easily to be understood, so you need to know the tricks how to get it working). Moreover, in order to get fast over such a design task, it needs a person with good experience with similar designs.

All this needs an education procedure which is provided by high schools and/or text book studies, which take quite a while, and which surely cannot be covered within the framework of a forum. Analog designers who can manage such a design still need some time to get it working - and get paid for such tasks.

What you want will take hours if not days to get it working, also depending under which environmental conditions (re. PVT ranges) the design should work - in an individual technology process with full PDK support and available design and analysis tools set up - even for an experienced designer.

Now decide if you will learn and manage it yourself, or get an analog designer to have it done - not me, BTW!
Good luck, anyway!