unable to create IOpowr padring using Sroute in SOCEncounter

[asic_engg]

Hi
For our ASIC, we have a set of core power pads that supply 1.8v to core area and another set of IO power pads that supply 3.3vto IO pads.

We are able to do successful Sroute to connect std_cells VCC& GND to core power/ground nets and to the COre power pad pins.

However, when I do sroute for creating pad ring, I get the following error
"**WARN: (SOCSR-1255): Net power does not have pad pins to create pad
ring. Please check net list or port class. (must NOT be CORE class and
must not be AREAIO subclass).

here is the snippet of io.lef for IO power pad
MACRO VCC3IOD
CLASS PAD ;
FOREIGN VCC3IOD 0.000 0.000 ;
ORIGIN 0.000 0.000 ;
SIZE 62.620 BY 140.120 ;
SYMMETRY x y r90 ;
SITE iocore_d ;
PIN VCC3O
DIRECTION INOUT ;
USE ANALOG ;
PORT
LAYER metal6 ;
RECT 2.850 0.000 59.770 3.000 ;
LAYER metal5 ;
RECT 2.850 0.000 59.770 3.000 ;
LAYER metal4 ;
RECT 2.850 0.000 59.770 3.000 ;
LAYER metal3 ;
RECT 2.850 0.000 59.770 3.000 ;
LAYER metal2 ;
RECT 2.850 0.000 59.770 3.000 ;
LAYER metal1 ;
RECT 2.850 0.000 59.770 3.000 ;
END
END VCC3O

Can anybody please tell me what could be wrong?
Do I need to specify different power/ground nets for IO pad ring? Do I need to modify .lef file? DO i need to associate pad pins to IO power/ground nets in GlobalConnect?
I've tried but still it fails.

Thanks

 

[research235]

dear asic_eng

i wll try to answer ur question though not sure if this is the correct one.

There are generally 2 kind of supplies for a ful l.. IO's power and standar cell power. The standar cell power is less compared to IO's power.

The io pads which are attached to io pins these days have a layout which as more than one metal later running arround. so wen insert all the io pads. the empty spaces in btw the ios are also filled with dummy pads so that it as well connected metal around the core area.
SO for the final supplies each of the metal layer is connected to core supply and io supply and hence there is no need for any special routng .
this offcouse depends on the lib. vendor. Please try to contact them, they can help u in chip finishing

BR

SING

 

[h.edaboard]

first, use globalRoute to connect power nets with power pins, Or, alternatively, use CPF design create power net, bind power net with certain power pin, without such info, SOC Encounter will fail connecting power rail with the command sroute.

 

[asic_engg]

FYI, first I use GlobalConnect to associate
1. power net with core power pad pin
2. power net with std cell power pin
Then I do sroute, which gives the warning for unable to create pad ring for IO power pad.

Also, in .lef file, IO pads do not have power pins.
Kindly help in correctly doing the IO power routing

 

[iwpia50s]

Unless the naming convention is strange, I think your 3.3V to the IO PADs doesn't match the PAD you are using, which seems to be 3V.

 

[cop02ia]

Re: unable to create IOpowr padring using Sroute in SOCEncou

Hi,

AFAIK, pad rings (nowadays) are usually connected by abutting pads since they have power & ground (both IO & core) rails going across the pads (in the X-direction) as explained by research235.

I think the errors appear because you define IO power & ground as global connects.
From the few designs I've worked on, this is not needed since abutting pads (or overlapping depending on the IO filler pads make out as specified by library vendor documentation) is sufficient to connect pad rings.
Only core power & ground is used as global connects.

With all respect, I'd like to ask: have you physically seen how the pad rings look like? They can't be seen by the P&R tools which only rely on LEF information - and I think there's no indication of error in your LEF.

Best regards.

 

[asic_engg]

Hi Cop02ia
Thanks for the info.
As per your suggestion, I removed "IOpower" & "IOground" global connects.
I abutted the pads together by inserting IOfillers.
I only used "power" & "ground" global connects for core power.
On doing Sroute, core power routing passes as earlier, but still I get the same warning message that "Net power does not have pad pins to create pad ring".
Do you mean to say that this warning message should be ignored and the pad ring would have been created which is not visible in SOC Encounter?

Also, I observe that in my io.lef file, the IO pads have no apparent vdd/vss pins. Can this be an issue for the appearance of the warning message.

Thanks

 

[h.edaboard]

asic_engg,

looks like your lef file is incomplete, "USE POWER" must appear in the lef file so that the tool would be able to recognise its a power pin, I'm not 100% sure about this, give it a try!