barjaktar
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Hello.
I started working within a project where I am supposed to do some analog design. Since the only analog design that I have done so far was what I did in school, I have a very steep learning curve right now. I am trying very hard, but I have a lot of question on my mind. First I would like to solve my dilemmas about parameters. I hope you guys will find time to help me.
I've scanned through numerous pdfs that came with the UMC 130nm process design kit (PDK), and I was able to find out the threshold voltage, dielectric thickness, dielectric constant and so on. Unfortunately, I am unable to find what is the doping level of the substrate, what is the electrone and hole mobility through the channel and what are the values of the parasitic capacitances. I am interested into exact values that this model/technology uses.
Would you be so kind to help me out and tell me where I can find these values?
Thank you.
I started working within a project where I am supposed to do some analog design. Since the only analog design that I have done so far was what I did in school, I have a very steep learning curve right now. I am trying very hard, but I have a lot of question on my mind. First I would like to solve my dilemmas about parameters. I hope you guys will find time to help me.
I've scanned through numerous pdfs that came with the UMC 130nm process design kit (PDK), and I was able to find out the threshold voltage, dielectric thickness, dielectric constant and so on. Unfortunately, I am unable to find what is the doping level of the substrate, what is the electrone and hole mobility through the channel and what are the values of the parasitic capacitances. I am interested into exact values that this model/technology uses.
Would you be so kind to help me out and tell me where I can find these values?
Thank you.
