ultra low power flip flop

[jcpu]

any one doing ultra low power (low voltage as well) flip flop.
Please advise,:

 

[phdbreak]

what a coincidence. I read a book yesterday. it has some chapters focus on low power flip flop, such as double edge trigger, low input cap on clock signal, and etc. It's name is "Low power CMOS Circuits technology: Logic Design and CAD Tools".

there are several low power optimization strategies for flip-flop. some of them are not very practical, depending on your design. maybe you should provide more information about your goal, like clock tree power, leakage power, speed requirement.