To answer your question, first important thing we have to know is what's your target device. Is it a FPGA or ASIC?
Ans to Q1 :- If its FPGA then in data sheet you will get the FF delay before hand. If its ASIC then foundry will share this data with you.
Ans to Q2 :- It all depend upon you design. You have to have a understanding of you design. NOTHING else will help you out for detecting multi-cycle path.
Ans to Q3 :- As I said you will have data from either data sheet or foundry, and you understand you have understanding of design. Now, clock frequency can be estimated.
I hope this will help.