depanwita
Newbie level 4

I need to develop UART transmitter in VHDL(FPGA to PC through RS232). I have the following code in verilog. Can anyone please provide the corresponding VHDL code or any other code for implementing the desired one.
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 module transmitter1(clk,reset,transmit,data,TxD); input clk,reset,transmit; input[7:0] data; output TxD; reg TxD; reg [3:0] bitcounter; reg [12:0] counter; reg state, nextstate; reg [10:0] rightshiftreg; reg shift,load,clear; always @(posedge clk) begin if (reset) begin state<=0; counter<=0; bitcounter<=0; end else begin counter<=counter+1; if (counter>=1) begin state<=nextstate; counter<=0; if(load) rightshiftreg<={1'b1,^data,data,1'b0}; if(clear) bitcounter<=0; if(shift) begin rightshiftreg<=rightshiftreg>>1; bitcounter<=bitcounter+1; end end end end always @(state or bitcounter or transmit) begin load<=0; shift<=0; clear<=0; TxD<=1; case(state) 0: begin if(transmit==1) begin nextstate<=1; load<=1; shift<=0; clear<=0; end else begin nextstate<=0; TxD<=1; end end 1: begin if(bitcounter>=10)begin nextstate<=0; clear<=1; end else begin nextstate<=1; shift<=1; TxD<=rightshiftreg[0]; end end endcase end endmodule
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