pfaisalbe
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Hi I did a verilog design for UART.
Design It works well real case and simulation at 100 MHZ , 921600 baud rate. If I use the clock frequency as 80 MHz with baud rate 921600 ,
it does not work. Simulation is also not correct.
Any clue , where should I correct
Thanks in advance
F
Design It works well real case and simulation at 100 MHZ , 921600 baud rate. If I use the clock frequency as 80 MHz with baud rate 921600 ,
it does not work. Simulation is also not correct.
Any clue , where should I correct
Thanks in advance
F