UART RECEIVER problem

[pfaisalbe]

Hi I did a verilog design for UART.

Design It works well real case and simulation at 100 MHZ , 921600 baud rate. If I use the clock frequency as 80 MHz with baud rate 921600 ,

it does not work. Simulation is also not correct.

Any clue , where should I correct

Thanks in advance

F

 

[FvM]

I guess, you are using an unsuitable clock divider.

 

[pfaisalbe]

Thanks .I am using DCM to multiply 40 MHz to 80 MHz.

Oversampling process is not working at 80 MHz with this baudrate

Kind Regards

 

[FvM]

Oversampling process is not working at 80 MHz with this baudrate.

I think, it can work well, but some intelligency is needed in modifying the design.

FPGA designs have the advantage, that you're not restricted to standard oversampling ratios of e.g. 16. Alternatively, you can use a fractional frequency divider, which is utilized b.t.w. in many modern microprocessors, e.g. TI MSP430.

 

[pfaisalbe]

Thanks.

Yes I follow you. Does that mean for various baud rate design needs to change ? .


Any clue ?

Regards

Faisal