UART RECEIVER Controller

[karthik87]

Hi

Im writing code for rx side of UART and im using clock which is 16 times faster than Tx side...do i require to sample it,if so how to do it....???

and also let me know how to check for frame,overrun and parity errors

Thanks in advance

 

[Sckoarn]

karthik87,
You doing this in VHDL?
You wait for the falling edge of the start bit. Count 8 clocks, now you are in the center of the bit period, assuming the info you provided above. (that one bit is 16 clocks wide) Now start a counter that counts to 16, and sample the bit stream at each rollover for 8 data bits, your parity and how ever many stop bits you have. Go back to waiting for falling edge of input data (start bit). You can put other logic in that will test for framing, once you have collected the data, and parity, enter the stop bit state, if the input data has a falling edge before the stop bit(s) have finished, you can trigger an error. Parity is easy.

The above is off the top of my head, you could implement all that in a state machine.

Hope that helps
Sckoarn

 

[Alexium]

I agree, simple divider by 16 (with counter) might just solve the problem.
P.S. Sckoarn, I think what you described actually is a state machine, only of a non-standard description :smile:

 

[Sckoarn]

Alexium,
I can type relatively fast, so I tent to maybe type too much. I am not sure I understand your reply
"+1 for simple divider by 16 (using counter)."

Seems you do not type enough, I find that statement confusing.

I have some code that does this, in VHDL, but it is baudrate adaptive and runs off a higher clock (50M).

Sckoarn

 

[Alexium]

Sckoarn,
You're right, sometimes more words is better, sorry. By "+1" I meant "I second that". I'm not sure if this expression is used in modern English, but it is in Slavic.