uart in spartan 3an (vhdl)

[Pravinspidy]

hey try in open cores.org

 

[ambar686]

hi !! i was designing a full adder using two half adder using the following program, but constantly i got the same error. please help me. any suggestion is acceptable.

the name of vhd file is fulladd.vhd.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fulladd is
Port ( a1 : in STD_LOGIC;
b1 : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
car : out STD_LOGIC);
end fulladd;

architecture fullad of fulladd is
component ha
port(a: in std_logic;
b: in std_logic;
sha,cha: out std_logic);
end component;
signal s1,c1,c2:std_logic;
begin
H1: ha port map(a1,b1,s1,c1);
H2: ha port map(s1,cin,sum,c2);
car<=c1 or c2;

end fullad;


the ERROR i m getting is:
ERROR:NgdBuild:604 - logical block 'H1' with type 'ha' could not be resolved. A
pin name misspelling can cause this, a missing edif or ngc file, or the
misspelling of a type name. Symbol 'ha' is not supported in target
'xa9500xl'.
ERROR:NgdBuild:604 - logical block 'H2' with type 'ha' could not be resolved. A
pin name misspelling can cause this, a missing edif or ngc file, or the
misspelling of a type name. Symbol 'ha' is not supported in target
'xa9500xl'.

https://obrazki.elektroda.pl/4190037900_1378089675.png

https://obrazki.elektroda.pl/9776619300_1378089676.png