type of operation this verilog prog is performing?

[rohit.dignity]

'define CM_8 8'b11111111
'define C0_8 8'b00000000
module PCSADD;
input [15:0] a;
input [ 7:0] b;
output [15:0] r;

reg [15:0] v1, v2;
reg [15:0] r;//+
begin
v1 = a;
if( b[7] == 1'b1 )
v2 = {`CM_8, b};
else
v2 = {`C0_8, b};
v1 = v1 + v2;
r = v1;
end
endmodule