Type conversion (to UNSIGNED) can not have aggregate operand VHDL error

[markkthemk]

Hey Guys,

This is my first time posting on this website so bear with me.
I am a new user to VHDL so I don't know much about it.

For my studies I have a getting started to help me learn VHDL.
The problem is that there is a bug in the provided code.

This code is supposed to provide a test set to see what will happen to outputs a and b (if i understand correctly).
It also shows how to write particular parts of the code in different ways.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


entity stim_a_groter_b is
    Port ( a,b : out  STD_LOGIC_VECTOR (3 downto 0));
end stim_a_groter_b;

architecture Behavioral of stim_a_groter_b is

begin
  process
      constant maximum_integer_a : integer := 2**4-1;
      constant max_int_b : integer := 2**b'length-1;
  begin
    for i in 0 to maximum_integer_a loop
      for j in 0 to max_int_b loop
        a <= std_logic_vector(unsigned(i,4));
        b <= std_logic_vector(unsigned(j,b'length));
        wait for 10 ns;
    end loop;
  end loop;
  report "klaar" severity note;
  wait;
end process;     

end Behavioral;

The problem lies in the following 2 lines

a <= std_logic_vector(unsigned(i,4));
b <= std_logic_vector(unsigned(j,b'length));

giving these error messages (compiled in ModelSim 10.1b student version):

stim_a_groter_b.vhd(19): Type conversion (to UNSIGNED) can not have aggregate operand.
stim_a_groter_b.vhd(19): Illegal type conversion to ieee.std_logic_1164.STD_LOGIC_VECTOR (operand type is not known).
stim_a_groter_b.vhd(20): Type conversion (to UNSIGNED) can not have aggregate operand.
stim_a_groter_b.vhd(20): Illegal type conversion to ieee.std_logic_1164.STD_LOGIC_VECTOR (operand type is not known).
stim_a_groter_b.vhd(28): VHDL Compiler exiting


I'm pretty sure other people have also had this error. I have googled it a bit and found some problems/answers. However, I don't know enough about the language yet to actually interpret the answers in a way that I can use them.



I hope you will be able to help me

Mark.

 

[FboDigit]

Try using

a <= std_logic_vector(to_unsigned(i,4));
b <= std_logic_vector(to_unsigned(j,b'length));

Hope it help !

 

[markkthemk]

thank you FboDigit!

that did the trick

Mark.