TX_DATA_WIDTH of GT_FIBRE_CHAN_INST attribute

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beba001

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Hi.
What mind this code in verilog:

// synthesis attribute TX_DATA_WIDTH of GT_FIBRE_CHAN_INST is "1"


Thanks for your help.
 

Re: Verilog code

It is actually not related to Verilog HDL language. It is a constraint attribute for logic synthesis especially Xilinx FPGA XST synthesis.

You can search the style of entering the constraints from attached doc.
 

Re: Verilog code

Synthesis attributes for Verilog HDL and VHDL are also commonly called pragmas. These attributes are not standard Verilog HDL or VHDL commands; synthesis tools use
attributes to control the synthesis process in a particular manner. Attributes always apply to a specific design element, and are applied in the HDL source code.

The attribute you specified may control the width of the signal and set it to a width of '1'.
 

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