Two transistor forward with LTC3765/LTC3766?

[cupoftea]

Hi,

I am trying to get a 2 transistor forward working with the LTC3765/LTC3766 combo, in LTspice.
(I have high voltage reset so max duty can be >50%)

The LTspice simulation of this combo runs almost insanely slowly on my 8GB Laptop. (Huawei Matebook D)
The LTC3766 datasheet says max duty cycle is 80%. The LTC3765 says the max duty is 70%. So I presume it will be 70% max.(?).

Also, there is a “ripple rejection” feature with this chipset. This seems to be a means of keeping the output current clamped to a certain, chosen level when the output is overloaded. I have simply disabled this for this simulation.

There is a feature for inferring the magnetising current ramp on the forward stroke….however, I have disabled this since I simply have a 1100V reset voltage so that magnetising current always resets.
There is also a v.us clamp pin (VSEC pin), but I have disabled this too.

There is also a facility to sense current in the synchronous FET (I call it the freewheel FET). But again I have disabled this.
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Anyway, I am noticing that at certain times of the simulation, the “synchronous” FET is staying on for longer than a switching period…this surely should never be allowed?

Also, there are huge switching current spikes in the synchronous FETs…and this cannot be resolved no matter how the delay resistors are adjusted.
Also, the sec side forward synch fet comes on before the primary FET…and this should surely never happen?.....surely the sec side forward synch fet should only cone on after its diode has started conducting?

Do you have any way of righting this sim?.....even any way of speeding it up?…it is ridiculously slow.

--- Updated Jun 25, 2023 ---

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Also, the primary FET has the usual source sense resistor. However, in this case, if ever the primary current hits the current sense threshold (150mV), then the converter goes into fault, shuts down, then hiccups back ON. As you know, this is a very poor way to do things. As the LTC3765 datasheet explains, the soft start capacitor must be correctly set so that the source current sense threshold never gets breached at start up. (or else it wont start up!). But what about no_load_to_full_load transient, when the soft start capacitor is fully charged?……..i suppose its just tough…..the converter will go into endless hiccupping……quite something when you’ve payed >£12 for the LTC3765/LTC3766 combo.

--- Updated Jun 25, 2023 ---

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Originally, we were hoping to use this chip, with some extra circuitry, to do an offline synchronous two transistor forward converter. However, due to the modus operandi of these chips, this simply wont be possible. So it continues, there is no bona-fide chip or chipset on the market today, for doing a bona fide offline synchronous two transistor forward converter.

--- Updated Jun 25, 2023 ---

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Not only that, but >£12 for a chipset that doesnt even bother to limit the "synchronous " FET on time to less than the switchind period??? (in certain situations).

 

[cupoftea]

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It looks like the VSEC pin can possibly be used by an external oscillator to limit the duty cycle to 0.5. ie, use the PG drive to start the oscillator, at 0V, then go to , say 1V , to terminate the primary switch ON cycle.(?)

 

[cupoftea]

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So the attached makes LTC3765/LTC3766 amenable to use for offline Two Transistor forward. However, it wouldnt be of any use, because as can be seen, when it goes into no load, the inductor current reverses like mad in the freewheel synch FET....This dicharges Cout and makes Vout go totally unstable.
Also, again, the Primary FET comes ON after the secondary forward synch FET....and this is simply wrong.
So after all that, a solution for "2 Tran Fwd with sync rects" has not been found.
It would be better if the LTC3766 allowed one to disable the synch FETs...then they could be disabled in light load, so that the inductor current doesnt reverse in light load...but the LTC3766 does not offer this.
Amazed this chipset costs so much.
And thats not to mention the enormous spike currents seen.....i have removed leakage inductance, but that was because the sim is insanely slow when you include that.
So, does anyone know of a chip or chipset that can do offline synchronous Two Tran forward?

 

[cupoftea]

Also, regarding VS+ pin on LTC3766, its got a max of 16v....so that means you can t do inductor ripple cancellation if vout >16V?

 

[cupoftea]

They have a number of demo sims on the website, but they show PG coming ON well before SWB has gone to zero volts.....so cant the delays be suitably adjusted?.....we are running out of time to play with these sims as they run so slow.
With one of their provided sims of LTC3765/LTC3766, when you change the coupling factor k from 1 to 0.999, it drops out when it does its full to no load transient.
In fact, it actually drops out before that, when it goes from no to full load.

 

[cupoftea]

The modus operandi of the LTC3766 appears to be as follows….

*…PG FET is never allowed to be ON at same time as SG FET.

*…SG FET is only allowed to turn OFF a short instant after FG FET has turned ON. (this is in case there is reverse current in the SG FET…..which would mean breaking an inductive current….however, the diversionary path through the transformer secondary contains the transformer leakage inductance, which will give a voltage spike in response to the sudden di/dt)

*…PT+ “_|” edge makes active clamp gate turn OFF.

*…A PGD delay then turns primary power FET ON when its drain has fallen to Vin.

*….The FG FET is turned ON after the SWB node (its drain) has decayed to zero.

*….FG FET tends to come ON before the PGD FET, though there appears no reason why this must be the case (other than the cancellation of any slight interval of conduction by the parallel diode)

*…The SG FET is turned ON after the SGD delay, which should ensure that the SW pin (its drain) has fallen to zero volts before SG FET is turned ON.

*…The FG FET turns OFF at exactly the same time that the SG FET turns ON…(this again appears to be because of the fear of the breaking of any reversing output inductor current…….(so this means that any series resistor in the gate of SG should not slow up SG FET turn-ON)….otherwise the two sync FETs will not be “ON at the same time”, as required......though again, we refer to the situation with transformer leakage inductance here.

The above modus operandi is shown in diagram form on page 11 of the LTC3766 datasheet. However, none of the provided simulations demonstrate the above behaviour, and none of the demo board write-ups show scope shots confirming the above behaviour.

Has anyone bought a demo board of LTC3765/LTC3766 and managed to demo all of the above modus operandi? ...Without ever overvoltaging the sync FETs. If so, what was the transformer leakage inductance and LP/LS?
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The following shows a fairly heavy "Optional" active snubber which it would be suggested, in some situations, would not be just "Optional".

https://www.analog.com/media/en/technical-documentation/user-guides/DC2199AAFA.PDF

 

[BradtheRad]

when you change the coupling factor k from 1 to 0.999, it drops out when it does its full to no load transient.
In fact, it actually drops out before that, when it goes from no to full load.

Likewise in Falstad's simulator, if I reduce coupling coefficient from .999 (default value) to .998, it makes a surprisingly large drop in transformer efficiency. I don't know how accurately this reflects real life.