I want to design two stage op amp with n-mos input diff pair and I have one question,why the second stage of op amp is p-mos input common source and what can be if the socond stage is n-mos input common source?
The second stage is supposed to match the input load
current density at null so that Vds1=Vds2=Vds3. Any
other setup adds systematic mismatch (Vio, AVOL).
Besides this, putting a NMOS common-source stage
after the Ndiff/Pload pair will just not work right,
reliably. You would have a very hard time turning off
the common source NMOS except for a very limited
range of VIN+, as drain can go no lower than VIN+ - VTN.