Two questions about pipelined ADC design

[lhlbluesky]

first, i have designed a 1.5bit per stage pipelined adc, but i have a ergent problem: i use resistor ladder and buffer to generate vref+\vcm\vref-, when i simulate the whole adc,i find that the three voltage referrence settles slowly, and jitters sharply at the beginning ang end of every half clock cycle,what's the possible reason?
i use a capacitor to be parallel with the resistor ladder,but it improves little;
any possible reasons?pls help me.

second,i use smic 0.18um(1p4m) process, but when i add mim_tt model,the simulator(cadence spectre)reports error--undefined……what'sthe reason?how to solve it?anyone can help me?

thanks for reply.

 

[lladnar23]

about two questions

it might help to use less capacitance -- try to make the node faster, so that it settles in time. The other option is to use much more capacitance to reduce the impact from perturbations

 

[naalald]

Re: about two questions

Hi lhlbluesky,
Do you use convenient voltage buffers? You do need them!