I don't know. And because of this I'd look into the specifications.
Mainly:
* What voltage levels and drive strength is specified for the PS/2.
* then the FPGA datasheet: is the FPGA able to drive one ... or maybe even two PS/2 in parallel.
PS/2 data and clock lines are 5V level open collector signals (similar to I2C). Can't share clock between two ports, need to provide level converters for 3.3V FPGA IO.
PS/2 data and clock lines are 5V level open collector signals (similar to I2C). Can't share clock between two ports, need to provide level converters for 3.3V FPGA IO.