buenos
Advanced Member level 3
- Joined
- Oct 24, 2005
- Messages
- 960
- Helped
- 40
- Reputation
- 82
- Reaction score
- 24
- Trophy points
- 1,298
- Location
- Florida, USA
- Activity points
- 9,116
hi
i have 2 problems with timing analysis:
1.
For synchronous systems, i found in appnotes, that they calculate hold margins like this:
T_h_mar = T_o_delay - T_ih - T_skew
I dont understand why not this:
T_h_mar =T_clk/2 + T_o_delay - T_ih - T_skew
it seems in the first case, they want to change the data on the bus after the same clock edge, which samples in the receiver. I am talking about SDRAM (data/address) and DDR-SDRAM(address bus). As i know, they change the data at falling edge, and sample at rising edge, so the T_clk/2 should be there for the hold analysis, and also T_clk/2 at the setup analysis, instead of T_clk*1.
Am I correct?
2.
At DDR-SDRAM, what is Data output hold skew factor? (T_qhs)
i have 2 problems with timing analysis:
1.
For synchronous systems, i found in appnotes, that they calculate hold margins like this:
T_h_mar = T_o_delay - T_ih - T_skew
I dont understand why not this:
T_h_mar =T_clk/2 + T_o_delay - T_ih - T_skew
it seems in the first case, they want to change the data on the bus after the same clock edge, which samples in the receiver. I am talking about SDRAM (data/address) and DDR-SDRAM(address bus). As i know, they change the data at falling edge, and sample at rising edge, so the T_clk/2 should be there for the hold analysis, and also T_clk/2 at the setup analysis, instead of T_clk*1.
Am I correct?
2.
At DDR-SDRAM, what is Data output hold skew factor? (T_qhs)