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TVS specification procedure

stenzer

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Hi,

when reading TVS datasheets there are different (dependent) values listed i.e. clamping voltage V_CL, pulse peak current I_pp and and dynamic resistance R_D. Those values are stated for different conditons, usually for a 10/1000 µs and a 8/20 µs double exponential test pulse.

- I'm curious how this values are determined excactly, by means of test setup. E.g. is a voltage source with a defined output/series resistor connected to the TVS and its pulse peak voltage is varied?
- Is the maximum clamping voltage statistical evaluated? How is the maximum value "chosen"?
- Why is the maximum clamping voltage for a shorter test pulse (8/20 µs) higher than those of a longer one (10/1000 µs)? The dynamical resistance is lower for a short test pulse, so what "limits" the current through the TVS which is responsible for the high clamping voltage?

I'm thankful for any explanation and references to detailed literature.

BR
 

FvM

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The standard test pulses have a related generator specification, respectively well defined impedance.

Although the clamping voltage data refer to a pulse form, they mainly depend on the peak current. In so far you don't necessarily need the pulse spec to read the I/V characteristic.

The pulse form spec is important to define the absorbed energy.
 

stenzer

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Hi,

thank you for your replay.

The standard test pulses have a related generator specification, respectively well defined impedance.
I already thought so. Do you know an application node or similar literature where the testing and especially the equipment is described?
I almost only found literature regarding the wave form, not mentioning the test equipment and measurement setup.

Although the clamping voltage data refer to a pulse form, they mainly depend on the peak current. In so far you don't necessarily need the pulse spec to read the I/V characteristic.
I do not get that point completely. But I assume with a given dynamic resistance and an expected pulse current I can determine the resulting voltage. Nevertheless, R_D (if at all) is usually given for a specific pulse length e.g. for the SM30TY [1] in figure 6.

My biggest problem to understand is how this maximum clamping voltage emerges. To my understanding this is the highest voltage and therfore the latest voltage where the TVS clamps guaranteed. Thus, the voltage is the cause of the clamping and the current is its result.

The pulse form spec is important to define the absorbed energy.
But how to interpret other kind of wave forms e.g. determined by a SPICE simulation? Should the overall energy be compared with the area under a defined test pulse (10/1000 µs or 8/20 µs) as the maximum peak pulse power versus exponential pulse duration is usually given in the datasheet ([1] figure 4).


[1] https://www.st.com/resource/en/datasheet/sm30ty.pdf

BR
 

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The figure 5 curves in sm30ty datasheet show the opposite of what you assume in post #1. The clamping voltage increases with pulse width for a given pulse current. This behaviour is due to chip heating as far as I understand.

For the higher current range of the figure, the I/V curve isn't time invariant any more due to the large absorbed energy, other than I stated in post #2.

Regarding evaluation of the parameters, the diodes are connected to the respective test generator network, the capacitor is charged according to the applied test level and maximal pulse current and clamping voltage are recorded.
 

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Hi,

The figure 5 curves in sm30ty datasheet show the opposite of what you assume in post #1. The clamping voltage increases with pulse width for a given pulse current. This behaviour is due to chip heating as far as I understand.
Yes I agree if the current is given, but to my understanding the voltage causes the clamping, as V_CL is plotted on the abscissa. Thus for the same clamping voltage the shorter pulse results in a higher pulse peak current. Also the values listed in table 2 indicates the higher maximum clamping voltage for a shorther pulse e.g. for the SM30T28AY/CAY:

10/1000 µs: V_CL,max = 38.9 V, I_PP = 77.1 A, R_D = 0.140 \[\Omega\]
8/20 µs: V_CL,max = 50 V, I_PP = 660 A, R_D = 0.033 \[\Omega\]

For the higher current range of the figure, the I/V curve isn't time invariant any more due to the large absorbed energy, other than I stated in post #2.
Yes, as the dynamic resistance varies with pulse time t_p, thus changing during the whole clamping time. The dynamic resistance is given/stated in the datasheet for a certain pulse length t_p, which indicates a higher (ending) resistance for a longer t_p. So the clamping voltage is somewhat "constant" over the clamping period and the current decreases as the dynamic resistance increases over time.

Here I'm still confused, as the rising time of both test pulses are almost identical (8 µs vs. 10 µs) I would expect an almost identiacl initial R_D. Thus, I_pp should be similar as it is deterimined/emerging at the beginning of the clamping process (after 8 µs vs. 10 µs). So what is limiting those values for the individual tests? Is it the test generator itself?

Regarding evaluation of the parameters, the diodes are connected to the respective test generator network, the capacitor is charged according to the applied test level and maximal pulse current and clamping voltage are recorded.
Ok, so the test generator includes a capacitor, is that right? This capacitor is charged to a certain voltage which is higher than V_BR, than connected to the TVS and the resulting current and voltage across the TVS are recorded. I assume during this test only the cpacitor and the defined impedance (as mentioned in #2) are connected to the TVS.

BR
 

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