TSMC 350nm (High Voltage) VDD

[lambchops511]

The link is:
TSMC CL035HV Process


Is this correct-- this high voltage process can use 15V for VDD? Thanks.

 

[keith1200rs]

Correct, but you have to select the correct devices in the process and observe the design rules. The 'default' devices in the process as 3.3V.

Keith

 

[lambchops511]

Sorry-- this is really my first time working on fab-ing something.. What do you mean by "correct device" -- is this something I do in Cadence? Or is this something I do as a checkbox when I submit it to MOSIS later?

Many thanks.

 

[keith1200rs]

When you get the PDK and documentation you will find more than one NMOS transistor for example, probably quite a few. One will only work at 3.3V, one will work with the drain up to 15V, another with drain and source at 15V etc.

Keith

---------- Post added at 09:38 ---------- Previous post was at 09:37 ----------

... and you may not be able to use 0.35um width on the 15V devices.

 

[lambchops511]

Ah- Thank you. I am still on the SPICE simulation at this stage-- havent gotten the PDK yet. Thanks.

 

[keith1200rs]

You should be able to get the process documents and also HSpice models which should work on most Spice simulators (with a bit of tweaking maybe).

Keith