TSMC 0.35um ESD Size ??

[whitewiz]

mingkerdou

For the Power-rail ESD Clamp circuit(made by R,Moscap, PMOS,NMOS) for the LNA design, I can not find the paper about the size.

I am so wondering the size of the Clamp circuit(TSMC 0.35um Process).

Thank

Chris

 

[seanyang]

tsmc 0.35um esd

The RC decided the time you want to discharge the voltage.
And the last NMOS should be very big for the voltage you want discharge.
You can decide the size by simulation.

 

[hung_wai_ming@hotmail.com]

tsmc 0.35 esd

Hi whitewiz

Seems like you don't quite understand the ESD triggering using this approach. In order to be safer,
I suggest you to replace the final transistor to an NMOS transistor with gate connected to Vb, which is then a typical RC gate coupled structure for you to be more familiar with the basics first. Otherwise, you may fail finally in real silicon.
RC time constant should be not small to have enough discharge time for ESD, however, not too long to have inefficient power recycling during power on/off and hurts PAD layout area too much

 

[whitewiz]

What kind of simulation do I need to run and see how much the time does my lna spend ? I am so wondering the textbook from RFIC(Lee) or Design of Analog CMOS IC(Razavi) does not mention about the detail and papers too.

Thank you for your reply

The RC decided the time you want to discharge the voltage.
And the last NMOS should be very big for the voltage you want discharge.
You can decide the size by simulation.

 

[seanyang]

I think you can see "ESD in silicon integrated circuit" book.
You can find your answer.

 

[hung_wai_ming@hotmail.com]

Check for this guy MingKerDou. He is a professional in ESD and I think he is already one of the very best in this field.
He has published numerous papers and patents and his design is more practical than other designers or researchers. The papers from this guy can help you

 

[prcken]

Ming-Dou Ker actually
^^

 

[sissi]

as i know the rc value is an experiential value.