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i want to sketch multi-m multi-finger transistor layout for an NMOS transistor. Is below picture true?
pls hlp. how do i need to edit it?
I see in this layout, some blinking rectangles on poly with their diagonals. Is there any error?
No answer to my question?! pls hlp.
The uploaded picture is for a nmos2v transistor that has layed out by cadence layout. It has:
finger=5 and m=5
the gates are connected via POLY pathes.
pls tell me is it a true layout?
I don't think this is a problem. I constantly got these warnings when joining the gate terminals of transistors having gate contacts on both sides.
It a warning, like the one on the schematic when 4 or more wires join on the same point.
But then again I don't see the reason to break the transistor in so many pieces.