true transistor layout?

[april1975]

HELLO
i want to sketch multi-m multi-finger transistor layout for an NMOS transistor. Is below picture true?

pls hlp. how do i need to edit it?
I see in this layout, some blinking rectangles on poly with their diagonals. Is there any error?

 

[april1975]

Hello
No answer to my question?! pls hlp.
The uploaded picture is for a nmos2v transistor that has layed out by cadence layout. It has:
finger=5 and m=5
the gates are connected via POLY pathes.
pls tell me is it a true layout?

 

[lamoun]

Hello,

I don't think this is a problem. I constantly got these warnings when joining the gate terminals of transistors having gate contacts on both sides.
It a warning, like the one on the schematic when 4 or more wires join on the same point.

But then again I don't see the reason to break the transistor in so many pieces.

 

[april1975]

Hello lamoun
You wrote:

But then again I don't see the reason to break the transistor in so many pieces.

Do you have a better solution?
Do you say that I instance a MOS with 25 finger? Isn't it a very long trnsistor?
I'm newbie in layout and so I appreciate any direction. tnx

 

[keith1200rs]

It is not how I would expect a fingered layout to look. Something like this is more like I would expect:

**broken link removed**

Keith

 

[april1975]

hello keith
do you have created drain and source pathes in differnt metal layers?

 

[lamoun]

Do you have a better solution?
Do you say that I instance a MOS with 25 finger? Isn't it a very long trnsistor?

Not 25 fingers. 5 finger but with 5*W.
Same as if you stick the 5 transistors together.
This would be more compact than the layout you already have.

 

[keith1200rs]

Maybe something like this will help:

Keith