That makes sense and I think I can make due with that for a proof-of-concept. Although I'm clearly missing something. This code works in simulation:
//Buffer the input clock to be available for the another bank (limits clock rate to ??)
clock_generator_ddr_s8_diff #(
.S (S),
.DIFF_TERM ("FALSE"))
inst_clkgen(
.clkin_p (clkin_p),
.clkin_n (clkin_n),
.ioclkap (ioclkap),
.ioclkan (ioclkan),
.serdesstrobea (serdesstrobea),
.gclk (gclk));
//Clock Input. Generate ioclocks via BUFIO2
serdes_1_to_n_clk_ddr_s8_diff #(
.S (S), // Set the serdes factor
.DIFF_TERM ("TRUE")) // Enable or disable diff termination
inst_clkin (
.clkin_p (ioclkap),
.clkin_n (ioclkan),
.rxioclkp (rxioclkp),
.rxioclkn (rxioclkn),
.rx_serdesstrobe (rx_serdesstrobe),
.rx_bufg_x1 (rx_bufg_x1));
// Data Inputs
serdes_1_to_n_data_ddr_s8_diff #(
.S (S),
.D (D),
.DIFF_TERM ("TRUE")) // Enable or disable diff termination
inst_datain (
.use_phase_detector (1'b1), // '1' enables the phase detector logic
.datain_p (datain_p),
.datain_n (datain_n),
.rxioclkp (rxioclkp),
.rxioclkn (rxioclkn),
.rxserdesstrobe (rx_serdesstrobe),
.gclk (rx_bufg_x1),
.bitslip (bslip),
.reset (rst),
.data_out (rxd),
.debug_in (2'b00),
.debug ());
But when I try to implement the design I get the error that ERROR:NgdBuild:770 - IBUFDS 'IBUFDS' and IBUFDS 'IBUFDS_0' on net 'ioclkap' are
lined up in series. Buffers of the same direction cannot be placed in series. So, the translate failed. Can someone translate this for me?
On a brighter note, we are hiring a consultant that may be able to help me with some of these issues so I won't be so helpless!