jasonxilion
Junior Member level 1
we wanna design a fractional pll with ring oscillator.
the input frequency is from 5M to 50M, and we set the bandwith to be 50khz, the segma-delta modulator is 3th order. the current ICP is varying with the N which varies from 1 to 128
the troble we meet is by calculation the Cs in the LPF is more than 1uF!, if we want the phase margin more than 50
the other problem is the variation of bandwith is very big according the variation of N. we can't ensure that the system be stable at worst case (taking corner into account)
those are really key issues in pll design. anyone discuss this topic with me?
the input frequency is from 5M to 50M, and we set the bandwith to be 50khz, the segma-delta modulator is 3th order. the current ICP is varying with the N which varies from 1 to 128
the troble we meet is by calculation the Cs in the LPF is more than 1uF!, if we want the phase margin more than 50
the other problem is the variation of bandwith is very big according the variation of N. we can't ensure that the system be stable at worst case (taking corner into account)
those are really key issues in pll design. anyone discuss this topic with me?